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Message-ID: <d1fadd8d-4b3d-38a4-1d26-e72e8eff8ff1@codeaurora.org>
Date: Mon, 24 Jun 2019 14:57:53 +0530
From: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
To: Suzuki K Poulose <suzuki.poulose@....com>,
mathieu.poirier@...aro.org, leo.yan@...aro.org, robh+dt@...nel.org,
devicetree@...r.kernel.org, alexander.shishkin@...ux.intel.com,
andy.gross@...aro.org, david.brown@...aro.org, mark.rutland@....com
Cc: rnayak@...eaurora.org, vivek.gautam@...eaurora.org,
sibis@...eaurora.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org
Subject: Re: [PATCHv3 1/1] coresight: Do not default to CPU0 for missing CPU
phandle
On 6/24/2019 1:56 PM, Suzuki K Poulose wrote:
> Sai,
>
> Thanks for getting this done.
>
> On 24/06/2019 04:36, Sai Prakash Ranjan wrote:
>> Coresight platform support assumes that a missing "cpu" phandle
>> defaults to CPU0. This could be problematic and unnecessarily binds
>> components to CPU0, where they may not be. Let us make the DT binding
>> rules a bit stricter by not defaulting to CPU0 for missing "cpu"
>> affinity information.
>>
>> Also in coresight etm and cpu-debug drivers, abort the probe
>> for such cases.
>>
>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
>
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@....com>
Thanks for the review Suzuki.
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