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Message-Id: <20190625164733.11091-14-jorge.ramirez-ortiz@linaro.org>
Date: Tue, 25 Jun 2019 18:47:32 +0200
From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@...aro.org>
To: jorge.ramirez-ortiz@...aro.org, sboyd@...nel.org,
bjorn.andersson@...aro.org, david.brown@...aro.org,
jassisinghbrar@...il.com, mark.rutland@....com,
mturquette@...libre.com, robh+dt@...nel.org, will.deacon@....com,
arnd@...db.de, horms+renesas@...ge.net.au, heiko@...ech.de,
sibis@...eaurora.org, enric.balletbo@...labora.com,
jagan@...rulasolutions.com, olof@...om.net
Cc: vkoul@...nel.org, niklas.cassel@...aro.org,
georgi.djakov@...aro.org, amit.kucheria@...aro.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org,
linux-arm-msm@...r.kernel.org, khasim.mohammed@...aro.org
Subject: [PATCH v3 13/14] arm64: dts: qcom: qcs404: Add DVFS support
Support dynamic voltage and frequency scaling on qcs404.
Co-developed-by: Niklas Cassel <niklas.cassel@...aro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@...aro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@...aro.org>
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 9569686dbc41..4b4ce0b5df76 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -34,6 +34,9 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&pms405_s3>;
};
CPU1: cpu@101 {
@@ -43,6 +46,9 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&pms405_s3>;
};
CPU2: cpu@102 {
@@ -52,6 +58,9 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&pms405_s3>;
};
CPU3: cpu@103 {
@@ -61,6 +70,9 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&pms405_s3>;
};
L2_0: l2-cache {
--
2.21.0
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