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Date: Tue, 25 Jun 2019 08:55:14 +0000 From: Parshuram Raju Thombare <pthombar@...ence.com> To: Russell King - ARM Linux admin <linux@...linux.org.uk> CC: "andrew@...n.ch" <andrew@...n.ch>, "nicolas.ferre@...rochip.com" <nicolas.ferre@...rochip.com>, "davem@...emloft.net" <davem@...emloft.net>, "f.fainelli@...il.com" <f.fainelli@...il.com>, "netdev@...r.kernel.org" <netdev@...r.kernel.org>, "hkallweit1@...il.com" <hkallweit1@...il.com>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Rafal Ciepiela <rafalc@...ence.com>, Anil Joy Varughese <aniljoy@...ence.com>, Piotr Sroka <piotrs@...ence.com> Subject: RE: [PATCH v5 4/5] net: macb: add support for high speed interface >> +static inline void gem_mac_configure(struct macb *bp, int speed) >> + switch (speed) { >> + case SPEED_1000: >> + gem_writel(bp, NCFGR, GEM_BIT(GBE) | >> + gem_readl(bp, NCFGR)); >> + break; >> + case SPEED_100: >> + macb_writel(bp, NCFGR, MACB_BIT(SPD) | >> + macb_readl(bp, NCFGR)); >What happens to the NCFGR register if we call mac_config() first for >a 1G speed, then 100M and finally 10M - what value does the NCFGR >register end up with? > >I suspect it ends up with both the GBE and SPD bits set, and that is >probably not what you want. No, In gem_mac_config GBE and SPD bits are always cleared before setting appropriate bits as per requested speed, duplex mode. Regards, Parshuram Thombare
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