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Date:   Wed, 26 Jun 2019 09:33:18 -0700 (PDT)
From:   David Miller <davem@...emloft.net>
To:     Jose.Abreu@...opsys.com
Cc:     linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
        Joao.Pinto@...opsys.com, peppe.cavallaro@...com,
        alexandre.torgue@...com
Subject: Re: [PATCH net-next 01/10] net: stmmac: dwxgmac: Enable EDMA by
 default

From: Jose Abreu <Jose.Abreu@...opsys.com>
Date: Wed, 26 Jun 2019 15:47:35 +0200

> @@ -122,6 +122,8 @@ static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
>  	}
>  
>  	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
> +	writel(GENMASK(29, 0), ioaddr + XGMAC_TX_EDMA_CTRL);
> +	writel(GENMASK(29, 0), ioaddr + XGMAC_RX_EDMA_CTRL);
>  }

This mask is magic and there is no indication what the bits mean and
in particular what it means to set bits 0 -- 29

You have to document what these bits mean and thus what these register
writes actually do.

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