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Message-ID: <alpine.DEB.2.21.9999.1906261325290.23534@viisi.sifive.com>
Date: Wed, 26 Jun 2019 13:27:51 -0700 (PDT)
From: Paul Walmsley <paul.walmsley@...ive.com>
To: Rob Herring <robh@...nel.org>
cc: linux-riscv@...ts.infradead.org,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] dt-bindings: riscv: resolve 'make dt_binding_check'
warnings
On Wed, 26 Jun 2019, Rob Herring wrote:
> On Wed, Jun 26, 2019 at 9:30 AM Paul Walmsley <paul.walmsley@...ive.com> wrote:
> >
> > Rob pointed out that one of the examples in the RISC-V 'cpus' YAML schema
> > results in warnings from 'make dt_binding_check'. Fix these.
> >
> > While here, make the whitespace in the second example consistent with the
> > first example.
> >
> > Signed-off-by: Paul Walmsley <paul.walmsley@...ive.com>
> > Cc: Rob Herring <robh@...nel.org>
> > ---
> > .../devicetree/bindings/riscv/cpus.yaml | 26 ++++++++++---------
> > 1 file changed, 14 insertions(+), 12 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index 27f02ec4bb45..f97a4ecd7b91 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -152,17 +152,19 @@ examples:
> > - |
> > // Example 2: Spike ISA Simulator with 1 Hart
> > cpus {
> > - cpu@0 {
> > - device_type = "cpu";
> > - reg = <0>;
> > - compatible = "riscv";
> > - riscv,isa = "rv64imafdc";
> > - mmu-type = "riscv,sv48";
> > - interrupt-controller {
> > - #interrupt-cells = <1>;
> > - interrupt-controller;
> > - compatible = "riscv,cpu-intc";
> > - };
> > - };
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + cpu@0 {
>
> This only works because you removed 'cpus' and therefore none of this
> schema is applied.
I'm not following you - could you point out where "cpus" was removed?
> > + device_type = "cpu";
> > + reg = <0>;
> > + compatible = "riscv";
>
> According to the schema, this is wrong. It should have 2 strings. Or
> the schema needs to allow this case, but 'riscv' is too vague to be
> very useful.
OK, I'll come up with something for Spike.
> Also, I noticed that there's still a riscv/cpus.txt. That should be
> removed and replaced with this file. Looks like the hart description
> at least should be copied over (into top-level 'description').
OK, will do that when I hear back from you.
- Paul
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