lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  PHC 
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Wed, 26 Jun 2019 11:30:56 +0530
From:   Vignesh Raghavendra <>
To:     <>
CC:     Boris Brezillon <>,
        <>, <>,
        Marek Vasut <>,
        Miquel Raynal <>,
        Richard Weinberger <>,
        Rob Herring <>,
        Sergei Shtylyov <>
Subject: Re: [PATCH v7 3/5] mtd: Add support for HyperBus memory devices

On 26/06/19 6:46 AM, wrote:
> Hi Vignesh,
>> Subject
>> [PATCH v7 3/5] mtd: Add support for HyperBus memory devices
>> Cypress' HyperBus is Low Signal Count, High Performance Double Data Rate
>> Bus interface between a host system master and one or more slave
>> interfaces. HyperBus is used to connect microprocessor, microcontroller,
>> or ASIC devices with random access NOR flash memory (called HyperFlash)
>> or self refresh DRAM (called HyperRAM).
>> Its a 8-bit data bus (DQ[7:0]) with  Read-Write Data Strobe (RWDS)
>> signal and either Single-ended clock(3.0V parts) or Differential clock
>> (1.8V parts). It uses ChipSelect lines to select b/w multiple slaves.
>> At bus level, it follows a separate protocol described in HyperBus
>> specification[1].
>> HyperFlash follows CFI AMD/Fujitsu Extended Command Set (0x0002) similar
>> to that of existing parallel NORs. Since HyperBus is x8 DDR bus,
>> its equivalent to x16 parallel NOR flash wrt bits per clock cycle. But
>> HyperBus operates at >166MHz frequencies.
>> HyperRAM provides direct random read/write access to flash memory
>> array.
>> But, HyperBus memory controllers seem to abstract implementation details
>> and expose a simple MMIO interface to access connected flash.
>> Add support for registering HyperFlash devices with MTD framework. MTD
>> maps framework along with CFI chip support framework are used to support
>> communicating with flash.
>> Framework is modelled along the lines of spi-nor framework. HyperBus
>> memory controller (HBMC) drivers calls hyperbus_register_device() to
>> register a single HyperFlash device. HyperFlash core parses MMIO access
>> information from DT, sets up the map_info struct, probes CFI flash and
>> registers it with MTD framework.
>> Some HBMC masters need calibration/training sequence[3] to be carried
>> out, in order for DLL inside the controller to lock, by reading a known
>> string/pattern. This is done by repeatedly reading CFI Query
>> Identification String. Calibration needs to be done before trying to 
> detect
>> flash as part of CFI flash probe.
>> HyperRAM is not supported at the moment.
>> HyperBus specification can be found at[1]
>> HyperFlash datasheet can be found at[2]
>> [1]
>> [2]
>> [3]
>>     Table 12-5741. HyperFlash Access Sequence
>> Signed-off-by: Vignesh Raghavendra <>
> Cypress has announced the inclusion of Cypress’ high-bandwidth 
> HyperBus™ 8-bit serial memory interface into the new eXpanded SPI (xSPI) 
> electrical interface standard from the JEDEC Solid State Technology 
> Association 
> for detail, please goes to

Thanks for the link!
Announcement seems to be from March 2018 since then Cypress has
published detailed HyperBus protocol in public domain . Comparing JEDEC
xSPI specification and HyperBus protocol that Cypress has published,
they seem to be following 8D-8D-8D Profile 2.0 with Extended Command
Modifier of JEDEC xSPI spec.
Did you see anything missing/different?

I need to study xSPI spec in more detail, but seems like as long as we
support HyperBus Protocol spec from Cypress we should be safe.


Powered by blists - more mailing lists