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Message-ID: <20190626101228.GD6362@ulmo>
Date:   Wed, 26 Jun 2019 12:12:28 +0200
From:   Thierry Reding <thierry.reding@...il.com>
To:     Sowjanya Komatineni <skomatineni@...dia.com>
Cc:     jonathanh@...dia.com, tglx@...utronix.de, jason@...edaemon.net,
        marc.zyngier@....com, linus.walleij@...aro.org, stefan@...er.ch,
        mark.rutland@....com, pdeschrijver@...dia.com, pgaikwad@...dia.com,
        sboyd@...nel.org, linux-clk@...r.kernel.org,
        linux-gpio@...r.kernel.org, jckuo@...dia.com, josephl@...dia.com,
        talho@...dia.com, linux-tegra@...r.kernel.org,
        linux-kernel@...r.kernel.org, mperttunen@...dia.com,
        spatra@...dia.com, robh+dt@...nel.org, digetx@...il.com,
        devicetree@...r.kernel.org
Subject: Re: [PATCH V4 11/18] clk: tegra210: use fence_udelay during PLLU init

On Sun, Jun 23, 2019 at 08:02:52PM -0700, Sowjanya Komatineni wrote:
> This patch uses fence_udelay rather than udelay during PLLU
> initialization to ensure writes to clock registers happens before
> waiting for specified delay.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@...dia.com>
> ---
>  drivers/clk/tegra/clk-tegra210.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)

Acked-by: Thierry Reding <treding@...dia.com>

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