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Message-ID: <alpine.DEB.2.21.9999.1906260829030.21507@viisi.sifive.com>
Date: Wed, 26 Jun 2019 08:30:40 -0700 (PDT)
From: Paul Walmsley <paul.walmsley@...ive.com>
To: linux-riscv@...ts.infradead.org
cc: linux-kernel@...r.kernel.org, robh@...nel.org
Subject: [PATCH] dt-bindings: riscv: resolve 'make dt_binding_check'
warnings
Rob pointed out that one of the examples in the RISC-V 'cpus' YAML schema
results in warnings from 'make dt_binding_check'. Fix these.
While here, make the whitespace in the second example consistent with the
first example.
Signed-off-by: Paul Walmsley <paul.walmsley@...ive.com>
Cc: Rob Herring <robh@...nel.org>
---
.../devicetree/bindings/riscv/cpus.yaml | 26 ++++++++++---------
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 27f02ec4bb45..f97a4ecd7b91 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -152,17 +152,19 @@ examples:
- |
// Example 2: Spike ISA Simulator with 1 Hart
cpus {
- cpu@0 {
- device_type = "cpu";
- reg = <0>;
- compatible = "riscv";
- riscv,isa = "rv64imafdc";
- mmu-type = "riscv,sv48";
- interrupt-controller {
- #interrupt-cells = <1>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- };
- };
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv48";
+ interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
};
...
--
2.20.1
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