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Message-Id: <20190627182114.27299-2-paul@crapouillou.net>
Date: Thu, 27 Jun 2019 20:21:13 +0200
From: Paul Cercueil <paul@...pouillou.net>
To: David Airlie <airlied@...ux.ie>, Daniel Vetter <daniel@...ll.ch>
Cc: Sam Ravnborg <sam@...nborg.org>, dri-devel@...ts.freedesktop.org,
linux-kernel@...r.kernel.org, od@...c.me,
Paul Cercueil <paul@...pouillou.net>
Subject: [PATCH 2/3] DRM: ingenic: Add support for Sharp panels
Add support for the LCD panels that must be driven with the
Sharp-specific signals SPL, CLS, REV, PS.
An example of such panel is the LS020B1DD01D supported by the
panel-simple DRM panel driver.
Signed-off-by: Paul Cercueil <paul@...pouillou.net>
---
drivers/gpu/drm/ingenic/ingenic-drm.c | 64 +++++++++++++++++----------
1 file changed, 41 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c b/drivers/gpu/drm/ingenic/ingenic-drm.c
index 02c4788ef1c7..da966f3dc1f7 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm.c
@@ -166,6 +166,8 @@ struct ingenic_drm {
struct ingenic_dma_hwdesc *dma_hwdesc;
dma_addr_t dma_hwdesc_phys;
+
+ bool panel_is_sharp;
};
static const u32 ingenic_drm_primary_formats[] = {
@@ -283,6 +285,13 @@ static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv,
regmap_write(priv->map, JZ_REG_LCD_DAV,
vds << JZ_LCD_DAV_VDS_OFFSET |
vde << JZ_LCD_DAV_VDE_OFFSET);
+
+ if (priv->panel_is_sharp) {
+ regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1));
+ regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1));
+ regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1));
+ regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16);
+ }
}
static void ingenic_drm_crtc_update_ctrl(struct ingenic_drm *priv,
@@ -378,11 +387,18 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
{
struct ingenic_drm *priv = drm_encoder_get_priv(encoder);
struct drm_display_mode *mode = &crtc_state->adjusted_mode;
- struct drm_display_info *info = &conn_state->connector->display_info;
- unsigned int cfg = JZ_LCD_CFG_PS_DISABLE
- | JZ_LCD_CFG_CLS_DISABLE
- | JZ_LCD_CFG_SPL_DISABLE
- | JZ_LCD_CFG_REV_DISABLE;
+ struct drm_connector *conn = conn_state->connector;
+ struct drm_display_info *info = &conn->display_info;
+ unsigned int cfg;
+
+ priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS;
+
+ if (priv->panel_is_sharp) {
+ cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY;
+ } else {
+ cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE
+ | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
+ }
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
@@ -393,24 +409,26 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
- if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) {
- if (mode->flags & DRM_MODE_FLAG_INTERLACE)
- cfg |= JZ_LCD_CFG_MODE_TV_OUT_I;
- else
- cfg |= JZ_LCD_CFG_MODE_TV_OUT_P;
- } else {
- switch (*info->bus_formats) {
- case MEDIA_BUS_FMT_RGB565_1X16:
- cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT;
- break;
- case MEDIA_BUS_FMT_RGB666_1X18:
- cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
- break;
- case MEDIA_BUS_FMT_RGB888_1X24:
- cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
- break;
- default:
- break;
+ if (!priv->panel_is_sharp) {
+ if (conn->connector_type == DRM_MODE_CONNECTOR_TV) {
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+ cfg |= JZ_LCD_CFG_MODE_TV_OUT_I;
+ else
+ cfg |= JZ_LCD_CFG_MODE_TV_OUT_P;
+ } else {
+ switch (*info->bus_formats) {
+ case MEDIA_BUS_FMT_RGB565_1X16:
+ cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT;
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X18:
+ cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
+ break;
+ default:
+ break;
+ }
}
}
--
2.21.0.593.g511ec345e18
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