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Message-ID: <0e33a1f2-f535-91e3-635d-dc8852833a0b@codeaurora.org>
Date:   Thu, 27 Jun 2019 23:51:56 +0530
From:   Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
To:     Mathieu Poirier <mathieu.poirier@...aro.org>
Cc:     Suzuki K Poulose <suzuki.poulose@....com>,
        Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
        Leo Yan <leo.yan@...aro.org>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        David Brown <david.brown@...aro.org>,
        Mark Rutland <mark.rutland@....com>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        Vivek Gautam <vivek.gautam@...eaurora.org>,
        Sibi Sankar <sibis@...eaurora.org>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>
Subject: Re: [RESEND PATCHv4 1/1] coresight: Do not default to CPU0 for
 missing CPU phandle

On 6/27/2019 10:54 PM, Mathieu Poirier wrote:
> 
> I want to apply your code to my tree but it isn't easy for me to do
> so.  Did you notice the checkpatch.pl warning about the DT bindings
> being in a separate patch?  In this case it is not a new binding but
> following the process gives the DT maintainers the opportunity to at
> least look at your patch.  Because the changes are trivial they may
> decide to ignore it but that choice it theirs to make.
> 

Hmm, git log on coresight dt-bindings showed some examples like
this where bindings were updated in the same patch.

Anyways, I have separated out the patch now and resent v5.

Thanks,
Sai

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