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Message-ID: <20190628160212.GB21829@e121166-lin.cambridge.arm.com>
Date: Fri, 28 Jun 2019 17:02:12 +0100
From: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
To: "Z.q. Hou" <zhiqiang.hou@....com>
Cc: "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"mark.rutland@....com" <mark.rutland@....com>,
"l.subrahmanya@...iveil.co.in" <l.subrahmanya@...iveil.co.in>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
Leo Li <leoyang.li@....com>,
"catalin.marinas@....com" <catalin.marinas@....com>,
"will.deacon@....com" <will.deacon@....com>,
Mingkai Hu <mingkai.hu@....com>,
"M.h. Lian" <minghuan.lian@....com>,
Xiaowei Bao <xiaowei.bao@....com>
Subject: Re: [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for
MEM inbound transactions
On Fri, Apr 12, 2019 at 08:36:00AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@....com>
>
> The inbound windows have independent register set against outbound windows.
> This patch change the MEM inbound window to the first one.
You mean that windows 0 can be used as well as window 1 for inbound
windows so it is better to opt for window 0 for consistency ?
Lorenzo
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@....com>
> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@...iveil.co.in>
> ---
> V5:
> - Corrected and retouched the subject and changelog.
>
> drivers/pci/controller/pcie-mobiveil.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> index df71c11b4810..e88afc792a5c 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -616,7 +616,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
>
> /* memory inbound translation window */
> - program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
> + program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
>
> /* Get the I/O and memory ranges from DT */
> resource_list_for_each_entry(win, &pcie->resources) {
> --
> 2.17.1
>
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