linux-kernel - RE: [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions

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Date:   Mon, 1 Jul 2019 10:18:35 +0000
From:   "Z.q. Hou" <zhiqiang.hou@....com>
To:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>
CC:     "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "l.subrahmanya@...iveil.co.in" <l.subrahmanya@...iveil.co.in>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        Leo Li <leoyang.li@....com>,
        "catalin.marinas@....com" <catalin.marinas@....com>,
        "will.deacon@....com" <will.deacon@....com>,
        Mingkai Hu <mingkai.hu@....com>,
        "M.h. Lian" <minghuan.lian@....com>,
        Xiaowei Bao <xiaowei.bao@....com>
Subject: RE: [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for MEM
 inbound transactions

Hi Lorenzo,

Thanks a lot for your comments!

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
> Sent: 2019年6月29日 0:02
> To: Z.q. Hou <zhiqiang.hou@....com>
> Cc: linux-pci@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> devicetree@...r.kernel.org; linux-kernel@...r.kernel.org;
> bhelgaas@...gle.com; robh+dt@...nel.org; mark.rutland@....com;
> l.subrahmanya@...iveil.co.in; shawnguo@...nel.org; Leo Li
> <leoyang.li@....com>; catalin.marinas@....com; will.deacon@....com;
> Mingkai Hu <mingkai.hu@....com>; M.h. Lian <minghuan.lian@....com>;
> Xiaowei Bao <xiaowei.bao@....com>
> Subject: Re: [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for
> MEM inbound transactions
> 
> On Fri, Apr 12, 2019 at 08:36:00AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@....com>
> >
> > The inbound windows have independent register set against outbound
> windows.
> > This patch change the MEM inbound window to the first one.
> 
> You mean that windows 0 can be used as well as window 1 for inbound
> windows so it is better to opt for window 0 for consistency ?

I mean the inbound windows and outbound windows are independent, they
have themselves' registers, and both serial number starts from 0:
Inbound windows: #0, #1, #2...
Outbound windows: #0, #1, #2... 

Thanks,
Zhiqiang

> Lorenzo
> 
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@....com>
> > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@...iveil.co.in>
> > ---
> > V5:
> >  - Corrected and retouched the subject and changelog.
> >
> >  drivers/pci/controller/pcie-mobiveil.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > b/drivers/pci/controller/pcie-mobiveil.c
> > index df71c11b4810..e88afc792a5c 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -616,7 +616,7 @@ static int mobiveil_host_init(struct mobiveil_pcie
> *pcie)
> >  			   CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
> >
> >  	/* memory inbound translation window */
> > -	program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE,
> IB_WIN_SIZE);
> > +	program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE,
> > +IB_WIN_SIZE);
> >
> >  	/* Get the I/O and memory ranges from DT */
> >  	resource_list_for_each_entry(win, &pcie->resources) {
> > --
> > 2.17.1
> >