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Message-ID: <20190703175601.GA14034@kroah.com>
Date: Wed, 3 Jul 2019 19:56:01 +0200
From: Greg KH <gregkh@...uxfoundation.org>
To: Moritz Fischer <mdf@...nel.org>
Cc: linux-fpga@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-doc@...r.kernel.org, Wu Hao <hao.wu@...el.com>,
Ananda Ravuri <ananda.ravuri@...el.com>,
Xu Yilun <yilun.xu@...el.com>, Alan Tull <atull@...nel.org>
Subject: Re: [PATCH 04/15] fpga: dfl: fme: support 512bit data width PR
On Thu, Jun 27, 2019 at 05:49:40PM -0700, Moritz Fischer wrote:
> From: Wu Hao <hao.wu@...el.com>
>
> In early partial reconfiguration private feature, it only
> supports 32bit data width when writing data to hardware for
> PR. 512bit data width PR support is an important optimization
> for some specific solutions (e.g. XEON with FPGA integrated),
> it allows driver to use AVX512 instruction to improve the
> performance of partial reconfiguration. e.g. programming one
> 100MB bitstream image via this 512bit data width PR hardware
> only takes ~300ms, but 32bit revision requires ~3s per test
> result.
>
> Please note now this optimization is only done on revision 2
> of this PR private feature which is only used in integrated
> solution that AVX512 is always supported. This revision 2
> hardware doesn't support 32bit PR.
>
> Signed-off-by: Ananda Ravuri <ananda.ravuri@...el.com>
> Signed-off-by: Xu Yilun <yilun.xu@...el.com>
> Signed-off-by: Wu Hao <hao.wu@...el.com>
> Acked-by: Alan Tull <atull@...nel.org>
> Signed-off-by: Moritz Fischer <mdf@...nel.org>
> ---
> drivers/fpga/dfl-fme-main.c | 3 +
> drivers/fpga/dfl-fme-mgr.c | 113 +++++++++++++++++++++++++++++++-----
> drivers/fpga/dfl-fme-pr.c | 43 +++++++++-----
> drivers/fpga/dfl-fme.h | 2 +
> drivers/fpga/dfl.h | 5 ++
> 5 files changed, 135 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
> index 086ad2420ade..076d74f6416d 100644
> --- a/drivers/fpga/dfl-fme-main.c
> +++ b/drivers/fpga/dfl-fme-main.c
> @@ -21,6 +21,8 @@
> #include "dfl.h"
> #include "dfl-fme.h"
>
> +#define DRV_VERSION "0.8"
> +
> static ssize_t ports_num_show(struct device *dev,
> struct device_attribute *attr, char *buf)
> {
> @@ -277,3 +279,4 @@ MODULE_DESCRIPTION("FPGA Management Engine driver");
> MODULE_AUTHOR("Intel Corporation");
> MODULE_LICENSE("GPL v2");
> MODULE_ALIAS("platform:dfl-fme");
> +MODULE_VERSION(DRV_VERSION);
No, we ripped out these useless "driver version" things all over the
place, please do not add them back in again. They mean nothing and
confuse people to no end.
I'll not take this patch, sorry.
greg k-h
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