linux-kernel - [tip:perf/core] perf jevents: Add support for Hisi hip08 L3C PMU aliasing

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Message-ID: <tip-edd93a4076cf18ede423c167de6d6fb8e4211e7b@git.kernel.org>
Date:   Wed, 3 Jul 2019 07:40:18 -0700
From:   tip-bot for John Garry <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     hpa@...or.com, alexander.shishkin@...ux.intel.com,
        mingo@...nel.org, namhyung@...nel.org, kan.liang@...ux.intel.com,
        john.garry@...wei.com, brueckner@...ux.ibm.com,
        mark.rutland@....com, zhangshaokun@...ilicon.com,
        peterz@...radead.org, ben@...adent.org.uk, ak@...ux.intel.com,
        jolsa@...nel.org, tglx@...utronix.de, linux-kernel@...r.kernel.org,
        tmricht@...ux.ibm.com, mathieu.poirier@...aro.org,
        will.deacon@....com, acme@...hat.com
Subject: [tip:perf/core] perf jevents: Add support for Hisi hip08 L3C PMU
 aliasing

Commit-ID:  edd93a4076cf18ede423c167de6d6fb8e4211e7b
Gitweb:     https://git.kernel.org/tip/edd93a4076cf18ede423c167de6d6fb8e4211e7b
Author:     John Garry <john.garry@...wei.com>
AuthorDate: Fri, 28 Jun 2019 22:35:52 +0800
Committer:  Arnaldo Carvalho de Melo <acme@...hat.com>
CommitDate: Tue, 2 Jul 2019 16:08:16 -0300

perf jevents: Add support for Hisi hip08 L3C PMU aliasing

Add support for Hisi hip08 L3C PMU aliasing.

The kernel driver is in drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c

Signed-off-by: John Garry <john.garry@...wei.com>
Acked-by: Jiri Olsa <jolsa@...nel.org>
Cc: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc: Andi Kleen <ak@...ux.intel.com>
Cc: Ben Hutchings <ben@...adent.org.uk>
Cc: Hendrik Brueckner <brueckner@...ux.ibm.com>
Cc: Kan Liang <kan.liang@...ux.intel.com>
Cc: Mark Rutland <mark.rutland@....com>
Cc: Mathieu Poirier <mathieu.poirier@...aro.org>
Cc: Namhyung Kim <namhyung@...nel.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Shaokun Zhang <zhangshaokun@...ilicon.com>
Cc: Thomas Richter <tmricht@...ux.ibm.com>
Cc: Will Deacon <will.deacon@....com>
Cc: linux-arm-kernel@...ts.infradead.org
Cc: linuxarm@...wei.com
Link: http://lkml.kernel.org/r/1561732552-143038-5-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@...hat.com>
---
 .../arch/arm64/hisilicon/hip08/uncore-l3c.json     | 37 ++++++++++++++++++++++
 tools/perf/pmu-events/jevents.c                    |  1 +
 2 files changed, 38 insertions(+)

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
new file mode 100644
index 000000000000..ca48747642e1
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
@@ -0,0 +1,37 @@
+[
+   {
+	    "EventCode": "0x00",
+	    "EventName": "uncore_hisi_l3c.rd_cpipe",
+	    "BriefDescription": "Total read accesses",
+	    "PublicDescription": "Total read accesses",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x01",
+	    "EventName": "uncore_hisi_l3c.wr_cpipe",
+	    "BriefDescription": "Total write accesses",
+	    "PublicDescription": "Total write accesses",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x02",
+	    "EventName": "uncore_hisi_l3c.rd_hit_cpipe",
+	    "BriefDescription": "Total read hits",
+	    "PublicDescription": "Total read hits",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x03",
+	    "EventName": "uncore_hisi_l3c.wr_hit_cpipe",
+	    "BriefDescription": "Total write hits",
+	    "PublicDescription": "Total write hits",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x04",
+	    "EventName": "uncore_hisi_l3c.victim_num",
+	    "BriefDescription": "l3c precharge commands",
+	    "PublicDescription": "l3c precharge commands",
+	    "Unit": "hisi_sccl,l3c",
+   },
+]
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 3c95affd85a4..287a6f10ca48 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -238,6 +238,7 @@ static struct map {
 	{ "UPI LL", "uncore_upi" },
 	{ "hisi_sccl,ddrc", "hisi_sccl,ddrc" },
 	{ "hisi_sccl,hha", "hisi_sccl,hha" },
+	{ "hisi_sccl,l3c", "hisi_sccl,l3c" },
 	{}
 };