linux-kernel - Re: [PATCH bpf-next] Enable zext optimization for more RV64G ALU ops

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Message-ID: <fbd0a41a-2d45-7b25-b417-f325d31c0074@iogearbox.net>
Date:   Sat, 6 Jul 2019 00:01:13 +0200
From:   Daniel Borkmann <daniel@...earbox.net>
To:     Luke Nelson <lukenels@...washington.edu>,
        linux-kernel@...r.kernel.org
Cc:     Luke Nelson <luke.r.nels@...il.com>,
        Song Liu <liu.song.a23@...il.com>,
        Jiong Wang <jiong.wang@...ronome.com>,
        Xi Wang <xi.wang@...il.com>,
        Björn Töpel <bjorn.topel@...il.com>,
        Palmer Dabbelt <palmer@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Alexei Starovoitov <ast@...nel.org>,
        Martin KaFai Lau <kafai@...com>,
        Song Liu <songliubraving@...com>, Yonghong Song <yhs@...com>,
        netdev@...r.kernel.org, linux-riscv@...ts.infradead.org,
        bpf@...r.kernel.org
Subject: Re: [PATCH bpf-next] Enable zext optimization for more RV64G ALU ops

On 07/05/2019 02:18 AM, Luke Nelson wrote:
> commit 66d0d5a854a6 ("riscv: bpf: eliminate zero extension code-gen")
> added the new zero-extension optimization for some BPF ALU operations.
> 
> Since then, bugs in the JIT that have been fixed in the bpf tree require
> this optimization to be added to other operations: commit 1e692f09e091
> ("bpf, riscv: clear high 32 bits for ALU32 add/sub/neg/lsh/rsh/arsh"),
> and commit fe121ee531d1 ("bpf, riscv: clear target register high 32-bits
> for and/or/xor on ALU32")
> 
> Now that these have been merged to bpf-next, the zext optimization can
> be enabled for the fixed operations.
> 
> Cc: Song Liu <liu.song.a23@...il.com>
> Cc: Jiong Wang <jiong.wang@...ronome.com>
> Cc: Xi Wang <xi.wang@...il.com>
> Signed-off-by: Luke Nelson <luke.r.nels@...il.com>

Applied, thanks!