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Message-ID: <CA+5LGR22k7cshDiiM=nv4BUtZko8JLoW3-ZjYgsdPkcedstDtQ@mail.gmail.com>
Date: Mon, 8 Jul 2019 09:28:53 +0300
From: Ilia Lin <ilia.lin@...nel.org>
To: Niklas Cassel <niklas.cassel@...aro.org>
Cc: Andy Gross <agross@...nel.org>, Ilia Lin <ilia.lin@...nel.org>,
Viresh Kumar <vireshk@...nel.org>, Nishanth Menon <nm@...com>,
Stephen Boyd <sboyd@...nel.org>, linux-arm-msm@...r.kernel.org,
jorge.ramirez-ortiz@...aro.org, bjorn.andersson@...aro.org,
ulf.hansson@...aro.org, Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>, linux-pm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 03/13] dt-bindings: cpufreq: qcom-nvmem: Make speedbin
related properties optional
Reviewed-by: Ilia Lin <ilia.lin@...nel.org>
On Fri, Jul 5, 2019 at 12:58 PM Niklas Cassel <niklas.cassel@...aro.org> wrote:
>
> Not all Qualcomm platforms need to care about the speedbin efuse,
> nor the value blown into the speedbin efuse.
> Therefore, make the nvmem-cells and opp-supported-hw properties
> optional.
>
> Signed-off-by: Niklas Cassel <niklas.cassel@...aro.org>
> ---
> Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
> index 198441e80ba8..c5ea8b90e35d 100644
> --- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
> +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
> @@ -20,6 +20,10 @@ In 'cpus' nodes:
> In 'operating-points-v2' table:
> - compatible: Should be
> - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
> +
> +Optional properties:
> +--------------------
> +In 'operating-points-v2' table:
> - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
> efuse registers that has information about the
> speedbin that is used to select the right frequency/voltage
> --
> 2.21.0
>
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