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Message-ID: <CABb+yY3OsAh3xgX8_vvA7A7mU+FkEj__BQs9CxMvf=eYxRYXyw@mail.gmail.com>
Date: Tue, 9 Jul 2019 23:12:03 -0500
From: Jassi Brar <jassisinghbrar@...il.com>
To: Rob Herring <robh@...nel.org>
Cc: dmaengine@...r.kernel.org,
Devicetree List <devicetree@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
vkoul@...nel.org, Mark Rutland <mark.rutland@....com>,
orito.takao@...ionext.com,
Masami Hiramatsu <masami.hiramatsu@...aro.org>,
kasai.kazuhiro@...ionext.com,
Jassi Brar <jaswinder.singh@...aro.org>
Subject: Re: [PATCH 1/2] dt-bindings: milbeaut-m10v-hdmac: Add Socionext
Milbeaut HDMAC bindings
On Tue, Jul 9, 2019 at 9:34 AM Rob Herring <robh@...nel.org> wrote:
>
> On Wed, Jun 12, 2019 at 07:52:37PM -0500, jassisinghbrar@...il.com wrote:
> > From: Jassi Brar <jaswinder.singh@...aro.org>
> >
> > Document the devicetree bindings for Socionext Milbeaut HDMAC
> > controller. Controller has upto 8 floating channels, that need
> > a predefined slave-id to work from a set of slaves.
> >
> > Signed-off-by: Jassi Brar <jaswinder.singh@...aro.org>
> > ---
> > .../bindings/dma/milbeaut-m10v-hdmac.txt | 54 +++++++++++++++++++
> > 1 file changed, 54 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/dma/milbeaut-m10v-hdmac.txt
> >
> > diff --git a/Documentation/devicetree/bindings/dma/milbeaut-m10v-hdmac.txt b/Documentation/devicetree/bindings/dma/milbeaut-m10v-hdmac.txt
> > new file mode 100644
> > index 000000000000..a104fcb9e73d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/milbeaut-m10v-hdmac.txt
> > @@ -0,0 +1,51 @@
> > +* Milbeaut AHB DMA Controller
> > +
> > +Milbeaut AHB DMA controller has transfer capability bellow.
> > + - memory to memory transfer
> > + - device to memory transfer
> > + - memory to device transfer
> > +
> > +Required property:
> > +- compatible: Should be "socionext,milbeaut-m10v-hdmac"
> > +- reg: Should contain DMA registers location and length.
> > +- interrupts: Should contain all of the per-channel DMA interrupts.
>
> How many?
>
Each channel has an IRQ line. And the number of channels is
configurable. So instead of having some explicit property like
'dma-channels', we infer that from the number of irqs registered.
> > +- #dma-cells: Should be 1. Specify the ID of the slave.
> > +- clocks: Phandle to the clock used by the HDMAC module.
> > +
> > +
> > +Example:
> > +
> > + hdmac1: hdmac@...10000 {
>
> dma-controller@...
>
OK
> > + compatible = "socionext,milbeaut-m10v-hdmac";
> > + reg = <0x1e110000 0x10000>;
> > + interrupts = <0 132 4>,
> > + <0 133 4>,
> > + <0 134 4>,
> > + <0 135 4>,
> > + <0 136 4>,
> > + <0 137 4>,
> > + <0 138 4>,
> > + <0 139 4>;
> > + #dma-cells = <1>;
> > + clocks = <&dummy_clk>;
> > + };
> > +
> > +* DMA client
> > +
> > +Clients have to specify the DMA requests with phandles in a list.
>
> Nothing specific to this binding here and the client side is already
> documented, so drop this section.
>
OK.
Thanks
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