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Message-ID: <20190710201433.GC35486@google.com>
Date: Wed, 10 Jul 2019 15:14:34 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: Vidya Sagar <vidyas@...dia.com>
Cc: lorenzo.pieralisi@....com, robh+dt@...nel.org,
mark.rutland@....com, thierry.reding@...il.com,
jonathanh@...dia.com, kishon@...com, catalin.marinas@....com,
will.deacon@....com, jingoohan1@...il.com,
gustavo.pimentel@...opsys.com, digetx@...il.com,
mperttunen@...dia.com, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
kthota@...dia.com, mmaddireddy@...dia.com, sagar.tv@...il.com
Subject: Re: [PATCH V13 01/12] PCI: Add #defines for some of PCIe spec r4.0
features
On Wed, Jul 10, 2019 at 11:52:01AM +0530, Vidya Sagar wrote:
> Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
> features as defined in PCIe spec r4.0, sec 7.7.4 for Data Link Feature and
> sec 7.7.5 for Physical Layer 16.0 GT/s.
>
> Signed-off-by: Vidya Sagar <vidyas@...dia.com>
> Reviewed-by: Thierry Reding <treding@...dia.com>
Acked-by: Bjorn Helgaas <bhelgaas@...gle.com>
Looks good, thanks!
> ---
> V13:
> * Updated commit message to include references from spec
> * Removed unused defines and moved some from pcie-tegra194.c file
> * Addressed review comments from Bjorn
>
> V12:
> * None
>
> V11:
> * None
>
> V10:
> * None
>
> V9:
> * None
>
> V8:
> * None
>
> V7:
> * None
>
> V6:
> * None
>
> V5:
> * None
>
> V4:
> * None
>
> V3:
> * Updated commit message and description to explicitly mention that defines are
> added only for some of the features and not all.
>
> V2:
> * None
>
> include/uapi/linux/pci_regs.h | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index f28e562d7ca8..d28d0319d932 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -713,7 +713,9 @@
> #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
> #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
> #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
> -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
> +#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
> +#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */
> +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT
>
> #define PCI_EXT_CAP_DSN_SIZEOF 12
> #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
> @@ -1053,4 +1055,14 @@
> #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */
> #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */
>
> +/* Data Link Feature */
> +#define PCI_DLF_CAP 0x04 /* Capabilities Register */
> +#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */
> +
> +/* Physical Layer 16.0 GT/s */
> +#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
> +#define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F
> +#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0
> +#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4
> +
> #endif /* LINUX_PCI_REGS_H */
> --
> 2.17.1
>
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