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Message-ID: <20190711153013.GP7234@tuxbook-pro>
Date: Thu, 11 Jul 2019 08:30:13 -0700
From: Bjorn Andersson <bjorn.andersson@...aro.org>
To: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@...aro.org>
Cc: sboyd@...nel.org, david.brown@...aro.org, jassisinghbrar@...il.com,
mark.rutland@....com, mturquette@...libre.com, robh+dt@...nel.org,
will.deacon@....com, arnd@...db.de, horms+renesas@...ge.net.au,
heiko@...ech.de, sibis@...eaurora.org,
enric.balletbo@...labora.com, jagan@...rulasolutions.com,
olof@...om.net, vkoul@...nel.org, niklas.cassel@...aro.org,
georgi.djakov@...aro.org, amit.kucheria@...aro.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org,
linux-arm-msm@...r.kernel.org, khasim.mohammed@...aro.org
Subject: Re: [PATCH v3 01/14] clk: qcom: gcc: limit GPLL0_AO_OUT operating
frequency
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware
> specifications.
>
> Co-developed-by: Niklas Cassel <niklas.cassel@...aro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@...aro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@...aro.org>
> Acked-by: Stephen Boyd <sboyd@...nel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> ---
> drivers/clk/qcom/clk-alpha-pll.c | 8 ++++++++
> drivers/clk/qcom/clk-alpha-pll.h | 1 +
> drivers/clk/qcom/gcc-qcs404.c | 2 +-
> 3 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 0ced4a5a9a17..ef51f302bdf0 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -730,6 +730,14 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
> return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
> }
>
> +const struct clk_ops clk_alpha_pll_fixed_ops = {
> + .enable = clk_alpha_pll_enable,
> + .disable = clk_alpha_pll_disable,
> + .is_enabled = clk_alpha_pll_is_enabled,
> + .recalc_rate = clk_alpha_pll_recalc_rate,
> +};
> +EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
> +
> const struct clk_ops clk_alpha_pll_ops = {
> .enable = clk_alpha_pll_enable,
> .disable = clk_alpha_pll_disable,
> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> index 66755f0f84fc..6b4eb74706b4 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.h
> +++ b/drivers/clk/qcom/clk-alpha-pll.h
> @@ -104,6 +104,7 @@ struct alpha_pll_config {
> };
>
> extern const struct clk_ops clk_alpha_pll_ops;
> +extern const struct clk_ops clk_alpha_pll_fixed_ops;
> extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
> extern const struct clk_ops clk_alpha_pll_postdiv_ops;
> extern const struct clk_ops clk_alpha_pll_huayra_ops;
> diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
> index 29cf464dd2c8..18c6563889f3 100644
> --- a/drivers/clk/qcom/gcc-qcs404.c
> +++ b/drivers/clk/qcom/gcc-qcs404.c
> @@ -330,7 +330,7 @@ static struct clk_alpha_pll gpll0_ao_out_main = {
> .parent_names = (const char *[]){ "cxo" },
> .num_parents = 1,
> .flags = CLK_IS_CRITICAL,
> - .ops = &clk_alpha_pll_ops,
> + .ops = &clk_alpha_pll_fixed_ops,
> },
> },
> };
> --
> 2.21.0
>
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