linux-kernel - [PATCH V2 1/2] usb: dwc3: Add node to update cache type setting

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Message-Id: <20190712064206.48249-1-ran.wang_1@nxp.com>
Date:   Fri, 12 Jul 2019 14:42:05 +0800
From:   Ran Wang <ran.wang_1@....com>
To:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Felipe Balbi <balbi@...nel.org>
Cc:     linux-usb@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, Ran Wang <ran.wang_1@....com>
Subject: [PATCH V2 1/2] usb: dwc3: Add node to update cache type setting

Some Layerscape paltforms (such as LS1088A, LS2088A, etc) encounter USB
detect failues when adding dma-coherent to DWC3 node. This is because the
HW default cache type configuration of those SoC are not right, need to
be updated in DTS.

Signed-off-by: Ran Wang <ran.wang_1@....com>
---
Change in v2:
	- New file.

 Documentation/devicetree/bindings/usb/dwc3.txt | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 8e5265e..7bc1cef 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -110,6 +110,43 @@ Optional properties:
  - in addition all properties from usb-xhci.txt from the current directory are
    supported as well
 
+* Cache type nodes (optional)
+
+The Cache type node is used to tell how to configure cache type on 4 different
+transfer types: Data Read, Desc Read, Data Write and Desc write. For each
+treasfer type, controller has a 4-bit register field to enable different cache
+type. Quoted from DWC3 data book Table 6-5 Cache Type Bit Assignments:
+----------------------------------------------------------------
+MBUS_TYPE| bit[3]       |bit[2]       |bit[1]     |bit[0]
+----------------------------------------------------------------
+AHB      |Cacheable     |Bufferable   |Privilegge |Data
+AXI3     |Write Allocate|Read Allocate|Cacheable  |Bufferable
+AXI4     |Allocate Other|Allocate     |Modifiable |Bufferable
+AXI4     |Other Allocate|Allocate     |Modifiable |Bufferable
+Native   |Same as AXI   |Same as AXI  |Same as AXI|Same as AXI
+----------------------------------------------------------------
+Note: The AHB, AXI3, AXI4, and PCIe busses use different names for certain
+signals, which have the same meaning:
+  Bufferable = Posted
+  Cacheable = Modifiable = Snoop (negation of No Snoop)
+
+In most cases, this node is not required unless the default values of related
+registers are not correct *and* DWC3 node has enabled dma-coherent. So far we
+have observed USB device detect failure on some Layerscape platforms if this
+programming is not conducted properly.
+
+Required properties:
+- transfer_type_datard:	A value for 4-bit register which decide cache type of
+  Data Read transfer. According to above table, we can know that different
+  master bus type will cause different definition of cache type control bit. So
+  developer need to know which master bus type his platforms are using in
+  advance, then decide the value for this transfer type.
+- transfer_type_descrd:	A value for 4-bit register which decide cache type of
+  Desc Read transfer.
+- transfer_type_datawr:	A value for 4-bit register which decide cache type of
+  Data Write transfer.
+- transfer_type_descwr:	A value for 4-bit register which decide cache type of
+  Desc Write transfer.
 
 This is usually a subnode to DWC3 glue to which it is connected.
 
@@ -119,4 +156,10 @@ dwc3@...30000 {
 	interrupts = <0 92 4>
 	usb-phy = <&usb2_phy>, <&usb3,phy>;
 	snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+	cache_type: cache_type {
+		transfer_type_datard = <0x2>;
+		transfer_type_descrd = <0x2>;
+		transfer_type_datawr = <0x2>;
+		transfer_type_descwr = <0x2>;
+	};
 };
-- 
2.7.4