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Message-Id: <dc04a9f8b234d7b0956a8d2560b8945bcd9c4bf7.1563117760.git.luto@kernel.org>
Date: Sun, 14 Jul 2019 08:23:14 -0700
From: Andy Lutomirski <luto@...nel.org>
To: LKML <linux-kernel@...r.kernel.org>
Cc: x86@...nel.org, Borislav Petkov <bp@...en8.de>,
Peter Zijlstra <peterz@...radead.org>,
Andy Lutomirski <luto@...nel.org>,
Nadav Amit <namit@...are.com>,
Stephane Eranian <eranian@...gle.com>,
Feng Tang <feng.tang@...el.com>,
Andrew Cooper <andrew.cooper3@...rix.com>
Subject: [PATCH] x86/apic: Initialize TPR to block interrupts 16-31
The APIC, per spec, is fundamentally confused and thinks that
interrupt vectors 16-31 are valid. This makes no sense -- the CPU
reserves vectors 0-31 for exceptions (faults, traps, etc).
Obviously, no device should actually produce an interrupt with
vector 16-31, but we can improve robustness by setting the APIC TPR
class to 1, which will prevent delivery of an interrupt with a
vector below 32.
Note: this is *not* intended as a security measure against attackers
who control malicious hardware. Any PCI or similar hardware that
can be controlled by an attacker MUST be behind a functional IOMMU
that remaps interrupts. The purpose of this patch is to reduce the
chance that a certain class of device malfunctions crashes the
kernel in hard-to-debug ways.
Cc: Nadav Amit <namit@...are.com>
Cc: Stephane Eranian <eranian@...gle.com>
Cc: Feng Tang <feng.tang@...el.com>
Suggested-by: Andrew Cooper <andrew.cooper3@...rix.com>
Signed-off-by: Andy Lutomirski <luto@...nel.org>
---
arch/x86/kernel/apic/apic.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 177aa8ef2afa..ff31322f8839 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1531,11 +1531,14 @@ static void setup_local_APIC(void)
#endif
/*
- * Set Task Priority to 'accept all'. We never change this
- * later on.
+ * Set Task Priority to 'accept all except vectors 0-31'. An APIC
+ * vector in the 16-31 range could be delivered if TPR == 0, but we
+ * would think it's an exception and terrible things will happen. We
+ * never change this later on.
*/
value = apic_read(APIC_TASKPRI);
value &= ~APIC_TPRI_MASK;
+ value |= 0x10;
apic_write(APIC_TASKPRI, value);
apic_pending_intr_clear();
--
2.21.0
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