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Message-Id: <20190715124417.4787-51-l.luba@partner.samsung.com>
Date: Mon, 15 Jul 2019 14:44:17 +0200
From: Lukasz Luba <l.luba@...tner.samsung.com>
To: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org
Cc: mturquette@...libre.com, sboyd@...nel.org,
b.zolnierkie@...sung.com, krzk@...nel.org, kgene@...nel.org,
mark.rutland@....com, robh+dt@...nel.org, cw00.choi@...sung.com,
kyungmin.park@...sung.com, a.hajda@...sung.com,
m.szyprowski@...sung.com, s.nawrocki@...sung.com,
myungjoo.ham@...sung.com, Lukasz Luba <l.luba@...tner.samsung.com>
Subject: [PATCH v1 50/50] ARM: dts: exynos: change MMC0 clock parent in
Exynos5800 Peach Pi
Change MMC0 clock settings and set parent to MOUT_SPLL with proper rate.
Signed-off-by: Lukasz Luba <l.luba@...tner.samsung.com>
---
arch/arm/boot/dts/exynos5800-peach-pi.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 38edb00c7f1b..c8e02ecc6627 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -891,6 +891,9 @@
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
+ assigned-clocks = <&clock CLK_MOUT_MMC0>, <&clock CLK_FOUT_SPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_SPLL>;
+ assigned-clock-rates = <0>, <800000000>;
};
&nocp_mem0_0 {
--
2.17.1
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