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Message-Id: <20190715124417.4787-22-l.luba@partner.samsung.com>
Date: Mon, 15 Jul 2019 14:43:48 +0200
From: Lukasz Luba <l.luba@...tner.samsung.com>
To: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org
Cc: mturquette@...libre.com, sboyd@...nel.org,
b.zolnierkie@...sung.com, krzk@...nel.org, kgene@...nel.org,
mark.rutland@....com, robh+dt@...nel.org, cw00.choi@...sung.com,
kyungmin.park@...sung.com, a.hajda@...sung.com,
m.szyprowski@...sung.com, s.nawrocki@...sung.com,
myungjoo.ham@...sung.com, Lukasz Luba <l.luba@...tner.samsung.com>
Subject: [PATCH v1 21/50] ARM: dts: exynos: add OPP into FSYS APB bus in
Exynos5420
Add an OPP for FSYS APB which reflects the real possible frequency.
The bus will have a new parent clock which speed has 600MHz, thus
a new possible frequency provided by the clock divider is 150MHz.
According to the documentation max possible frequency for this bus is
200MHz.
Signed-off-by: Lukasz Luba <l.luba@...tner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index c7fc4b829b2a..2b36c2f77a10 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1153,6 +1153,9 @@
opp-hz = /bits/ 64 <100000000>;
};
opp01 {
+ opp-hz = /bits/ 64 <150000000>;
+ };
+ opp02 {
opp-hz = /bits/ 64 <200000000>;
};
};
--
2.17.1
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