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Date:   Mon, 15 Jul 2019 14:43:39 +0200
From:   Lukasz Luba <l.luba@...tner.samsung.com>
To:     devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org
Cc:     mturquette@...libre.com, sboyd@...nel.org,
        b.zolnierkie@...sung.com, krzk@...nel.org, kgene@...nel.org,
        mark.rutland@....com, robh+dt@...nel.org, cw00.choi@...sung.com,
        kyungmin.park@...sung.com, a.hajda@...sung.com,
        m.szyprowski@...sung.com, s.nawrocki@...sung.com,
        myungjoo.ham@...sung.com, Lukasz Luba <l.luba@...tner.samsung.com>
Subject: [PATCH v1 12/50] clk: add ID to PWM MUX in Exynos5420

Add ID to PWM MUX to manage it from DT to reflect proper topology.

Signed-off-by: Lukasz Luba <l.luba@...tner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 7bf74401c4e7..7f8221527633 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -772,7 +772,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 	MUX(CLK_MOUT_UART1, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
 	MUX(CLK_MOUT_UART2, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
 	MUX(CLK_MOUT_UART3, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
-	MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
+	MUX(CLK_MOUT_PWM, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
 	MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
 	MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
 	MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
-- 
2.17.1

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