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Message-ID: <20190715141636.GB442@linux.intel.com>
Date: Mon, 15 Jul 2019 07:16:36 -0700
From: Sean Christopherson <sean.j.christopherson@...el.com>
To: Tao Xu <tao3.xu@...el.com>
Cc: pbonzini@...hat.com, rkrcmar@...hat.com, corbet@....net,
tglx@...utronix.de, mingo@...hat.com, bp@...en8.de, hpa@...or.com,
kvm@...r.kernel.org, linux-kernel@...r.kernel.org,
fenghua.yu@...el.com, xiaoyao.li@...ux.intel.com,
jingqi.liu@...el.com
Subject: Re: [PATCH v7 2/3] KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL
On Mon, Jul 15, 2019 at 09:22:14AM +0800, Tao Xu wrote:
> On 7/12/2019 11:52 PM, Sean Christopherson wrote:
> >The SDM only defines bits 31:0, and the kernel uses a u32 to cache its
> >value. I assume bits 63:32 are reserved? I'm guessing we also need an
> >SDM update...
> >
>
> The SDM define IA32_UMWAIT_CONTROL is a 32bit MSR. So need me to set 63:32
> reserved?
Huh, I didn't realize the SDM allows 32 bit MSRs, I assumed all bits
needed to be explicitly defined even if the underlying implementation only
tracked 32 bits.
RDMSR:
If fewer than 64 bits are implemented in the MSR being read, the values
return in EDX:EAX in unimplemented bit locations are undefined.
WRMSR:
Undefined or reserved bits in an MSR should be set to values previously
read.
>From KVM's perspective, bits 63:32 should be treated as reserved-to-zero.
This also means that struct vcpu_vmx can track a u32 instead of a u64
for msr_ia32_umwait_control.
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