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Message-ID: <CAL_JsqJ6o9mTjLYjnfcYgfSFKb95W8FseZBBb8RLosB__GNBcw@mail.gmail.com>
Date: Thu, 18 Jul 2019 10:40:21 -0600
From: Rob Herring <robh+dt@...nel.org>
To: Daniel Baluta <daniel.baluta@....com>
Cc: Shawn Guo <shawnguo@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Sascha Hauer <s.hauer@...gutronix.de>,
Sascha Hauer <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
NXP Linux Team <linux-imx@....com>,
"S.j. Wang" <shengjiu.wang@....com>, paul.olaru@....com,
Dong Aisheng <aisheng.dong@....com>,
Leonard Crestez <leonard.crestez@....com>,
Anson Huang <anson.huang@....com>, Peng Fan <peng.fan@....com>,
Frank Li <Frank.Li@....com>, devicetree@...r.kernel.org,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
sound-open-firmware@...a-project.org
Subject: Re: [PATCH 3/3] dt-bindings: dsp: fsl: Add DSP core binding support
On Thu, Jul 18, 2019 at 9:13 AM Daniel Baluta <daniel.baluta@....com> wrote:
>
> This describes the DSP device tree node.
>
> Signed-off-by: Daniel Baluta <daniel.baluta@....com>
> ---
> .../devicetree/bindings/dsp/fsl,dsp.yaml | 87 +++++++++++++++++++
> 1 file changed, 87 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
>
> diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
> new file mode 100644
> index 000000000000..d112486eda0e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
> @@ -0,0 +1,87 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/freescale/fsl,dsp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX8 DSP core
> +
> +maintainers:
> + - Daniel Baluta <daniel.baluta@....com>
> +
> +description: |
> + Some boards from i.MX8 family contain a DSP core used for
> + advanced pre- and post- audio processing.
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,imx8qxp-dsp
> +
> + reg:
> + description: Should contain register location and length
> +
> + clocks:
> + items:
> + - description: ipg clock
> + - description: ocram clock
> + - description: core clock
> +
> + clock-names:
> + items:
> + - const: ipg
> + - const: ocram
> + - const: core
> +
> + power-domains:
> + description:
> + List of phandle and PM domain specifier as documented in
> + Documentation/devicetree/bindings/power/power_domain.txt
How many? 4?
> +
> + mboxes:
> + description:
> + List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB
> + (see mailbox/fsl,mu.txt)
> + maxItems: 4
> +
> + mbox-names:
> + items:
> + - const: txdb0
> + - const: txdb1
> + - const: rxdb0
> + - const: rxdb1
> +
> + memory-region:
> + description:
> + phandle to a node describing reserved memory (System RAM memory)
> + used by DSP (see bindings/reserved-memory/reserved-memory.txt)
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - power-domains
> + - mboxes
> + - mbox-names
> + - memory-region
> +
> +examples:
> + - |
> + #include <dt-bindings/firmware/imx/rsrc.h>
> + #include <dt-bindings/clock/imx8-clock.h>
> + dsp@...e8000 {
> + compatbile = "fsl,imx8qxp-dsp";
> + reg = <0x596e8000 0x88000>;
> + clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
> + <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
> + <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
> + clock-names = "ipg", "ocram", "core";
> + power-domains = <&pd IMX_SC_R_MU_13A>,
> + <&pd IMX_SC_R_MU_13B>,
> + <&pd IMX_SC_R_DSP>,
> + <&pd IMX_SC_R_DSP_RAM>;
> + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
> + mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
> + };
> --
> 2.17.1
>
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