linux-kernel - Re: [PATCH 3/3] media: Add support for Cadence CSI2TX 2.1

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Date:   Mon, 22 Jul 2019 07:07:33 +0000
From:   Jan Kotas <jank@...ence.com>
To:     Maxime Ripard <maxime.ripard@...tlin.com>
CC:     Jan Kotas <jank@...ence.com>,
        "mchehab@...nel.org" <mchehab@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        linux-media <linux-media@...r.kernel.org>,
        linux-devicetree <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 3/3] media: Add support for Cadence CSI2TX 2.1



> On 20 Jul 2019, at 10:25, Maxime Ripard <maxime.ripard@...tlin.com> wrote:
> 
> Hi,
> 
> On Thu, Jul 18, 2019 at 12:15:09PM +0100, Jan Kotas wrote:
>> 	/* Put our lanes (clock and data) out of reset */
>> 	reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT;
>> 	for (i = 0; i < csi2tx->num_lanes; i++)
>> -		reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i]);
>> +		reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1);
> 
> This looks like a separate change?
> 
>> 	writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
>> 
>> -	udelay(10);
>> +	csi2tx_dphy_init_finish(csi2tx, reg);
>> +}
>> 
>> -	/* Enable our (clock and data) lanes */
>> -	reg |= CSI2TX_DPHY_CFG_CLK_ENABLE;
>> -	for (i = 0; i < csi2tx->num_lanes; i++)
>> -		reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i]);
> 
> And you have a similar change here that should be in a separate patch,
> with a proper explanation.
> 
> Otherwise, the rest looks good.

OK, I’ll create a separate patch with this modification.
Jan

> Maxime
> 
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com