lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <7610bbc9-83d8-ee98-1425-07bb65448541@intel.com>
Date:   Tue, 23 Jul 2019 08:20:15 +0300
From:   Adrian Hunter <adrian.hunter@...el.com>
To:     Alan Cooper <alcooperx@...il.com>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        linux-mmc <linux-mmc@...r.kernel.org>,
        ": Linux Kernel Mailing List" <linux-kernel@...r.kernel.org>
Subject: Re: Issue with sequence to switch to HS400

On 23/07/19 1:31 AM, Alan Cooper wrote:
> I'm having a problem with a new SD/MMC controller and PHY in our
> latest SoC's. The issue I'm seeing is that I can't switch into HS400
> mode. This looks like something the driver is doing that doesn't meet
> the JEDEC spec. In the "HS400 timing mode selection" section of the
> JEDEC spec , in step 7 it states:
> 
> 7) Set the “Timing Interface” parameter in the HS_TIMING [185] field
> of the Extended CSD register to 0x1 to switch to High Speed mode and
> then set the clock frequency to a value not greater than 52 MHz.
> 
> In the function mmc_select_hs400() in mmc.c, I see that a switch
> command is done to set the eMMC device to HS mode and then
> mmc_set_timing(card->host, MMC_TIMING_MMC_HS) is used to change the
> controller to HS mode. The problem is that the "SD Host Controller
> Standard Specification" states that "UHS Mode Select" field of the
> "Host Control 2 Register" controls the mode when the "1.8V Signaling
> Enable" bit in the same register is set, so mmc_set_timing() is
> actually leaving the controller in SDR12 mode and mmc_select_hs400()
> will then set the clock to 52MHz. This causes our PHY to detect an
> illegal combination and return an error.
> 
> I think the easiest fix would be to change mmc_set_timing(card->host,
> MMC_TIMING_MMC_HS) to mmc_set_timing(card->host,
> MMC_TIMING_UHS_SDR25). The other possibility would be to change
> mmc_set_timing to handle the "1.8V Signaling Enable" bit properly.
> I'll submit a patch based on the feedback I get.

eMMC is governed by JEDEC specs not SD specs.

Please consider making a change in your driver instead.  For example, hook
->set_ios() and if 1.8V is enabled and timing is set to MMC_TIMING_MMC_HS
then change it to MMC_TIMING_UHS_SDR25.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ