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Message-ID: <3fb07ff6-fd89-a42a-607a-1bce6a300805@samsung.com>
Date:   Tue, 23 Jul 2019 17:35:37 +0200
From:   Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>
To:     Manuel Lauss <manuel.lauss@...il.com>,
        Christoph Hellwig <hch@....de>
Cc:     Linux-MIPS <linux-mips@...r.kernel.org>,
        linux-fbdev <linux-fbdev@...r.kernel.org>,
        LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] au1200fb: don't use DMA_ATTR_NON_CONSISTENT


On 6/26/19 9:16 AM, Manuel Lauss wrote:
> On Tue, Jun 25, 2019 at 2:13 PM Christoph Hellwig <hch@....de> wrote:
>>
>> au1200fb allocates DMA memory using DMA_ATTR_NON_CONSISTENT, but never
>> calls dma_cache_sync to synchronize the memory between the CPU and the
>> device.  If it was use on a not cache coherent bus that would be fatal,
>> but as far as I can tell from the naming and the mips platform
>> implementation it always is used in cache coherent systems.  Remove
>> the DMA_ATTR_NON_CONSISTENT flag, which is a no-op in that case.
> 
> Very early au1200 chips, on which this driver apparently was developed on,
> had issues with cache coherency, but this was fixed in a later step,
> none of the 3 steppings I have access to exhibit any problems
> with this patch applied.
> 
>> Signed-off-by: Christoph Hellwig <hch@....de>
> 
> Acked-By: Manuel Lauss <manuel.lauss@...il.com>

Patch queued for v5.4, thanks.

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

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