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Message-ID: <20190724065530.GA16225@infradead.org>
Date:   Tue, 23 Jul 2019 23:55:30 -0700
From:   Christoph Hellwig <hch@...radead.org>
To:     Rob Clark <robdclark@...il.com>
Cc:     John Stultz <john.stultz@...aro.org>,
        Christoph Hellwig <hch@...radead.org>,
        lkml <linux-kernel@...r.kernel.org>,
        Laura Abbott <labbott@...hat.com>,
        Benjamin Gaignard <benjamin.gaignard@...aro.org>,
        Sumit Semwal <sumit.semwal@...aro.org>,
        Liam Mark <lmark@...eaurora.org>,
        Pratik Patel <pratikp@...eaurora.org>,
        Brian Starkey <Brian.Starkey@....com>,
        Vincent Donnefort <Vincent.Donnefort@....com>,
        Sudipto Paul <Sudipto.Paul@....com>,
        "Andrew F . Davis" <afd@...com>,
        Xu YiPing <xuyiping@...ilicon.com>,
        "Chenfeng (puck)" <puck.chen@...ilicon.com>,
        butao <butao@...ilicon.com>,
        "Xiaqing (A)" <saberlily.xia@...ilicon.com>,
        Yudongbin <yudongbin@...ilicon.com>,
        Chenbo Feng <fengc@...gle.com>,
        Alistair Strachan <astrachan@...gle.com>,
        dri-devel <dri-devel@...ts.freedesktop.org>,
        Hridya Valsaraju <hridya@...gle.com>
Subject: Re: [PATCH v6 2/5] dma-buf: heaps: Add heap helpers

On Tue, Jul 23, 2019 at 01:09:55PM -0700, Rob Clark wrote:
> On Mon, Jul 22, 2019 at 9:09 PM John Stultz <john.stultz@...aro.org> wrote:
> >
> > On Thu, Jul 18, 2019 at 3:06 AM Christoph Hellwig <hch@...radead.org> wrote:
> > >
> > > Is there any exlusion between mmap / vmap and the device accessing
> > > the data?  Without that you are going to run into a lot of coherency
> > > problems.
> 
> dma_fence is basically the way to handle exclusion between different
> device access (since device access tends to be asynchronous).  For
> device<->device access, each driver is expected to take care of any
> cache(s) that the device might have.  (Ie. device writing to buffer
> should flush it's caches if needed before signalling fence to let
> reading device know that it is safe to read, etc.)
> 
> _begin/end_cpu_access() is intended to be the exclusion for CPU access
> (which is synchronous)

What I mean is that we need a clear state machine (preferably including
ownership tracking ala dma-debug) where a piece of memory has one
owner at a time that can access it.  Only the owner can access is at
that time, and at any owner switch we need to flush/invalidate all
relevant caches.  And with memory that is vmaped and mapped to userspace
that can get really complicated.

The above sounds like you have some of that in place, but we'll really
need clear rules to make sure we don't have holes in the scheme.

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