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Message-Id: <20190725104144.22924-5-niklas.cassel@linaro.org>
Date: Thu, 25 Jul 2019 12:41:32 +0200
From: Niklas Cassel <niklas.cassel@...aro.org>
To: Andy Gross <agross@...nel.org>, Ilia Lin <ilia.lin@...nel.org>,
Viresh Kumar <vireshk@...nel.org>, Nishanth Menon <nm@...com>,
Stephen Boyd <sboyd@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, jorge.ramirez-ortiz@...aro.org,
bjorn.andersson@...aro.org, ulf.hansson@...aro.org,
Niklas Cassel <niklas.cassel@...aro.org>,
Rob Herring <robh@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>, linux-pm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH v2 04/14] dt-bindings: cpufreq: qcom-nvmem: Make speedbin related properties optional
Not all Qualcomm platforms need to care about the speedbin efuse,
nor the value blown into the speedbin efuse.
Therefore, make the nvmem-cells and opp-supported-hw properties
optional.
Signed-off-by: Niklas Cassel <niklas.cassel@...aro.org>
Reviewed-by: Ilia Lin <ilia.lin@...nel.org>
Reviewed-by: Rob Herring <robh@...nel.org>
---
Changes since V1:
-Picked up tags.
Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index 198441e80ba8..c5ea8b90e35d 100644
--- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -20,6 +20,10 @@ In 'cpus' nodes:
In 'operating-points-v2' table:
- compatible: Should be
- 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
+
+Optional properties:
+--------------------
+In 'operating-points-v2' table:
- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
efuse registers that has information about the
speedbin that is used to select the right frequency/voltage
--
2.21.0
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