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Message-ID: <CAGTfZH2UzvOVE-hKHLLGa7-ZF6DqsXvZiHcMy4O9qpohYLGbDA@mail.gmail.com>
Date: Thu, 25 Jul 2019 23:23:44 +0900
From: Chanwoo Choi <cwchoi00@...il.com>
To: Leonard Crestez <leonard.crestez@....com>
Cc: MyungJoo Ham <myungjoo.ham@...sung.com>,
Kyungmin Park <kyungmin.park@...sung.com>,
Will Deacon <will@...nel.org>, Stephen Boyd <sboyd@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Jacky Bai <ping.bai@....com>,
Anson Huang <Anson.Huang@....com>,
Abel Vesa <abel.vesa@....com>,
Dong Aisheng <aisheng.dong@....com>,
Viresh Kumar <viresh.kumar@...aro.org>,
Georgi Djakov <georgi.djakov@...aro.org>,
Alexandre Bailon <abailon@...libre.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
Mark Rutland <mark.rutland@....com>,
Frank Li <Frank.li@....com>, Rob Herring <robh+dt@...nel.org>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
NXP Linux Team <linux-imx@....com>,
Linux PM list <linux-pm@...r.kernel.org>,
devicetree <devicetree@...r.kernel.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [RFCv3 1/3] dt-bindings: devfreq: Add initial bindings for i.MX
Hi,
2019년 7월 24일 (수) 오후 10:36, Leonard Crestez <leonard.crestez@....com>님이 작성:
>
> Add initial dt bindings for the interconnects inside i.MX chips.
> Multiple external IPs are involved but SOC integration means the
> software controllable interfaces are very similar.
>
> This is initially only for imx8mm but add an "fsl,imx-bus" fallback
> similar to exynos-bus.
>
> Signed-off-by: Leonard Crestez <leonard.crestez@....com>
> ---
> .../devicetree/bindings/devfreq/imx.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/devfreq/imx.yaml
>
> diff --git a/Documentation/devicetree/bindings/devfreq/imx.yaml b/Documentation/devicetree/bindings/devfreq/imx.yaml
> new file mode 100644
> index 000000000000..87f90cddfd29
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/imx.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/devfreq/imx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Generic i.MX bus frequency device
> +
> +maintainers:
> + - Leonard Crestez <leonard.crestez@....com>
> +
> +description: |
> + The i.MX SoC family has multiple buses for which clock frequency (and sometimes
> + voltage) can be adjusted.
> +
> + Some of those buses expose register areas mentioned in the memory maps as GPV
> + ("Global Programmers View") but not all. Access to this area might be denied for
> + normal world.
> +
> + The buses are based on externally licensed IPs such as ARM NIC-301 and Arteris
> + FlexNOC but DT bindings are specific to the integration of these bus
> + interconnect IPs into imx SOCs.
> +
> +properties:
> + reg:
> + maxItems: 1
> + description: GPV area
> +
> + compatible:
> + contains:
> + enum:
> + - fsl,imx8m-noc
> + - fsl,imx8m-nic
> + - fsl,imx8m-ddrc
> +
> + clocks:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - clocks
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8mm-clock.h>
> + ddrc: dram-controller@...00000 {
> + compatible = "fsl,imx8mm-ddrc";
s/imx8mm/imx8m
> + reg = <0x3d400000 0x400000>;
> + clocks = <&clk IMX8MM_CLK_DRAM>;
> + operating-points-v2 = <&ddrc_opp_table>;
> + };
> +
> + - |
> + noc: noc@...00000 {
> + compatible = "fsl,imx8mm-noc";
s/imx8mm/imx8m
> + reg = <0x32700000 0x100000>;
> + clocks = <&clk IMX8MM_CLK_NOC>;
> + operating-points-v2 = <&noc_opp_table>;
> + };
> --
> 2.17.1
>
--
Best Regards,
Chanwoo Choi
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