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Message-ID: <alpine.DEB.2.21.9999.1907261625220.26670@viisi.sifive.com>
Date:   Fri, 26 Jul 2019 16:29:38 -0700 (PDT)
From:   Paul Walmsley <paul.walmsley@...ive.com>
To:     Atish Patra <atish.patra@....com>
cc:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Alan Kao <alankao@...estech.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Allison Randal <allison@...utok.net>,
        Anup Patel <Anup.Patel@....com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Johan Hovold <johan@...nel.org>,
        "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
        Palmer Dabbelt <palmer@...ive.com>,
        Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [PATCH 3/4] RISC-V: Support case insensitive ISA string
 parsing.

On Fri, 26 Jul 2019, Atish Patra wrote:

> On 7/26/19 1:47 PM, Paul Walmsley wrote:
> > On Fri, 26 Jul 2019, Atish Patra wrote:
> > 
> > > As per riscv specification, ISA naming strings are
> > > case insensitive. However, currently only lower case
> > > strings are parsed during cpu procfs.
> > > 
> > > Support parsing of upper case letters as well.
> > > 
> > > Signed-off-by: Atish Patra <atish.patra@....com>
> > 
> > Is there a use case that's driving this, or 
> 
> Currently, we use all lower case isa string in kvmtool. But somebody can have
> uppercase letters in future as spec allows it.
>
> 
> can we just say, "use
> > lowercase letters" and leave it at that?
> > 
> 
> In that case, it will not comply with RISC-V spec. Is that okay ?

I think that section of the specification is mostly concerned with someone 
trying to define "f" as a different extension than "F", or something like 
that.  I'm not sure that it imposes any constraint that software must 
accept both upper and lower case ISA strings.  

What gives me pause here is that this winds up impacting DT schema 
validation:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/cpus.yaml#n41



- Paul

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