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Message-Id: <20190726133936.11177-17-sashal@kernel.org>
Date:   Fri, 26 Jul 2019 09:38:27 -0400
From:   Sasha Levin <sashal@...nel.org>
To:     linux-kernel@...r.kernel.org, stable@...r.kernel.org
Cc:     Andy Gross <agross@...nel.org>,
        Niklas Cassel <niklas.cassel@...aro.org>,
        Vinod Koul <vkoul@...nel.org>, Olof Johansson <olof@...om.net>,
        Sasha Levin <sashal@...nel.org>, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org
Subject: [PATCH AUTOSEL 5.2 17/85] arm64: qcom: qcs404: Add reset-cells to GCC node

From: Andy Gross <agross@...nel.org>

[ Upstream commit 0763d0c2273a3c72247d325c48fbac3d918d6b87 ]

This patch adds a reset-cells property to the gcc controller on the QCS404.
Without this in place, we get warnings like the following if nodes reference
a gcc reset:

arch/arm64/boot/dts/qcom/qcs404.dtsi:261.38-310.5: Warning (resets_property):
/soc@...emoteproc@...000: Missing property '#reset-cells' in node
/soc@...lock-controller@...0000 or bad phandle (referred from resets[0])
  also defined at arch/arm64/boot/dts/qcom/qcs404-evb.dtsi:82.18-84.3
  DTC     arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb
arch/arm64/boot/dts/qcom/qcs404.dtsi:261.38-310.5: Warning (resets_property):
/soc@...emoteproc@...000: Missing property '#reset-cells' in node
/soc@...lock-controller@...0000 or bad phandle (referred from resets[0])
  also defined at arch/arm64/boot/dts/qcom/qcs404-evb.dtsi:82.18-84.3

Signed-off-by: Andy Gross <agross@...nel.org>
Reviewed-by: Niklas Cassel <niklas.cassel@...aro.org>
Reviewed-by: Vinod Koul <vkoul@...nel.org>
Signed-off-by: Olof Johansson <olof@...om.net>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index ffedf9640af7..65a2cbeb28be 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -383,6 +383,7 @@
 			compatible = "qcom,gcc-qcs404";
 			reg = <0x01800000 0x80000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 
 			assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
 			assigned-clock-rates = <19200000>;
-- 
2.20.1

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