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Message-ID: <b6506f6579f823e4c1e26ef3a7d1eed2@akkea.ca>
Date: Sun, 28 Jul 2019 07:53:08 -0700
From: Angus Ainslie <angus@...ea.ca>
To: Daniel Baluta <daniel.baluta@....com>
Cc: shawnguo@...nel.org, s.hauer@...gutronix.de, festevam@...il.com,
linux-imx@....com, l.stach@...gutronix.de, ccaione@...libre.com,
abel.vesa@....com, baruch@...s.co.il, andrew.smirnov@...il.com,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, shengjiu.wang@....com,
agx@...xcpu.org, Anson.Huang@....com,
linux-kernel-owner@...r.kernel.org
Subject: Re: [PATCH v3] arm64: dts: imx8mq: Init rates and parents configs for
clocks
Hi Daniel,
On 2019-07-28 07:12, Daniel Baluta wrote:
> From: Abel Vesa <abel.vesa@....com>
>
> Add the initial configuration for clocks that need default parent and
> rate
> setting. This is based on the vendor tree clock provider parents and
> rates
> configuration except this is doing the setup in dts rather then using
> clock
> consumer API in a clock provider driver.
>
> Note that by adding the initial rate setting for audio_pll1/audio_pll
> setting we need to remove it from imx8mq-librem5-devkit.dts
> imx8mq-librem5-devkit.dts
>
> Signed-off-by: Abel Vesa <abel.vesa@....com>
> Signed-off-by: Daniel Baluta <daniel.baluta@....com>
This works with our board. One small nit below
Tested-by: Angus Ainslie (Purism) <angus@...ea.ca>
> ---
> Changes since v2:
> - set rate for audio_pll1/audio_pll2 in the dtsi file and
> remove the setting from imx8mq-librem5-devkit.dts
>
> .../dts/freescale/imx8mq-librem5-devkit.dts | 5 -----
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 21 +++++++++++++++++++
> 2 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> index 683a11035643..c702ccc82867 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> @@ -169,11 +169,6 @@
> };
> };
>
> -&clk {
> - assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
> - assigned-clock-rates = <786432000>, <722534400>;
> -};
> -
> &dphy {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 02fbd0625318..c67625a881a4 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -494,6 +494,27 @@
> clock-names = "ckil", "osc_25m", "osc_27m",
> "clk_ext1", "clk_ext2",
> "clk_ext3", "clk_ext4";
> + assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1>,
> + <&clk IMX8MQ_AUDIO_PLL1>,
> + <&clk IMX8MQ_AUDIO_PLL2>,
> + <&clk IMX8MQ_CLK_AHB>,
> + <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
> + <&clk IMX8MQ_CLK_AUDIO_AHB>,
> + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
> + <&clk IMX8MQ_CLK_NOC>;
> + assigned-clock-parents = <0>,
> + <0>,
> + <0>,
> + <&clk IMX8MQ_SYS1_PLL_133M>,
> + <&clk IMX8MQ_SYS1_PLL_266M>,
> + <&clk IMX8MQ_SYS2_PLL_500M>,
> + <&clk IMX8MQ_CLK_27M>,
> + <&clk IMX8MQ_SYS1_PLL_800M>;
> + assigned-clock-rates = <593999999>,
> + <786432000>,
> + <722534400>;
> +
> +
Extra whitespace
Angus
> };
>
> src: reset-controller@...90000 {
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