lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Mon, 29 Jul 2019 17:19:23 -0400
From:   Paul Cercueil <paul@...pouillou.net>
To:     Uwe Kleine-König 
        <u.kleine-koenig@...gutronix.de>
Cc:     Thierry Reding <thierry.reding@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>, od@...c.me,
        linux-pwm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, kernel@...gutronix.de
Subject: Re: [PATCH v2 3/6] pwm: jz4740: Apply configuration atomically

Hi Uwe,


Le mer. 24 juil. 2019 à 2:47, Uwe =?iso-8859-1?q?Kleine-K=F6nig?= 
<u.kleine-koenig@...gutronix.de> a écrit :
> Hello Paul,
> 
> On Tue, Jul 23, 2019 at 04:46:40PM -0400, Paul Cercueil wrote:
>>  Le lun. 22 juil. 2019 à 15:34, Uwe =?iso-8859-1?q?Kleine-K=F6nig?=
>>  <u.kleine-koenig@...gutronix.de> a écrit :
>>  > On Fri, Jun 07, 2019 at 05:44:07PM +0200, Paul Cercueil wrote:
>>  > >  -	is_enabled = jz4740_timer_is_enabled(pwm->hwpwm);
>>  > >  -	if (is_enabled)
>>  > >  -		jz4740_pwm_disable(chip, pwm);
>>  > >  +	jz4740_pwm_disable(chip, pwm);
>>  >
>>  > I assume this stops the PWM. Does this complete the currently 
>> running
>>  > period? How does the PWM behave then? (Does it still drive the 
>> output?
>>  > If so, on which level?)
>> 
>>  Some PWM channels work in one mode "TCU1" and others work in 
>> "TCU2". The
>>  mode in which channels work depends on the version of the SoC.
>> 
>>  When stopped, the pins of TCU1 channels will be driven to the 
>> inactive
>>  level (which depends on the polarity). It is unknown whether or not 
>> the
>>  currently running period is completed. We set a bit to configure for
>>  "abrupt shutdown", so I expect that it's not, but somebody would 
>> need
>>  to hook up a logic analyzer to see what's the exact behaviour with
>>  and without that bit.
> 
> This might be done even without a logic analyzer. Just do something
> like:
> 
> 	pwm_apply_state(pwm, { .enabled = 1, .period = 5s })
> 	pwm_apply_state(pwm, { .enabled = 1, .period = 5s, .duty = 5s })
> 
> and if that takes less then 5s the period is not completed.
> 
> And note that "abrupt shutdown" is a bug.

I remember you asked that already in an older patchset.
The result of this test is that the period is never completed,
independently of the "abrupt shutdown" bit.

Cheers,
-Paul


>>  TCU2 channels on the other hand will stop in the middle of a period,
>>  leaving the pin hanging at whatever level it was before the stop.
>>  That's the rationale behind the trick in commit 6580fd173070 ("pwm:
>>  jz4740: Force TCU2 channels to return to their init level").
> 
> Strange, but ok.
> 
> Best regards
> Uwe
> 
> --
> Pengutronix e.K.                           | Uwe Kleine-König        
>     |
> Industrial Linux Solutions                 | 
> http://www.pengutronix.de/  |


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ