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Date: Mon, 29 Jul 2019 16:20:31 +0800 From: Roger Lu <roger.lu@...iatek.com> To: Kevin Hilman <khilman@...nel.org>, Rob Herring <robh+dt@...nel.org>, Nicolas Boichat <drinkcat@...gle.com>, Stephen Boyd <sboyd@...nel.org> CC: Fan Chen <fan.chen@...iatek.com>, HenryC Chen <HenryC.Chen@...iatek.com>, <yt.lee@...iatek.com>, Angus Lin <Angus.Lin@...iatek.com>, Mark Rutland <mark.rutland@....com>, Matthias Brugger <matthias.bgg@...il.com>, Nishanth Menon <nm@...com>, Roger Lu <roger.lu@...iatek.com>, <devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, <linux-mediatek@...ts.infradead.org>, <linux-kernel@...r.kernel.org>, <linux-pm@...r.kernel.org> Subject: [PATCH v4 1/2] dt-bindings: soc: add mtk svs dt-bindings Document the binding for enabling mtk svs on MediaTek SoC. Signed-off-by: Roger Lu <roger.lu@...iatek.com> --- .../devicetree/bindings/power/mtk-svs.txt | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/mtk-svs.txt diff --git a/Documentation/devicetree/bindings/power/mtk-svs.txt b/Documentation/devicetree/bindings/power/mtk-svs.txt new file mode 100644 index 000000000000..6a71992ef162 --- /dev/null +++ b/Documentation/devicetree/bindings/power/mtk-svs.txt @@ -0,0 +1,88 @@ +* Mediatek Smart Voltage Scaling (MTK SVS) + +This describes the device tree binding for the MTK SVS controller (bank) +which helps provide the optimized CPU/GPU/CCI voltages. This device also +needs thermal data to calculate thermal slope for accurately compensate +the voltages when temperature change. + +Required properties: +- compatible: + - "mediatek,mt8183-svs" : For MT8183 family of SoCs +- reg: Address range of the MTK SVS controller. +- interrupts: IRQ for the MTK SVS controller. +- clocks, clock-names: Clocks needed for the svs controller. required + clocks are: + "main_clk": Main clock needed for register access +- nvmem-cells: Phandle to the calibration data provided by a nvmem device. +- nvmem-cell-names: Should be "svs-calibration-data" and "calibration-data" + +Subnodes: +- svs_cpu_little: SVS bank device node of little CPU + compatible: "mediatek,mt8183-svs-cpu-little" + operating-points-v2: OPP table hooked by SVS little CPU bank. + SVS will optimze this OPP table voltage part. + vcpu-little-supply: PMIC buck of little CPU +- svs_cpu_big: SVS bank device node of big CPU + compatible: "mediatek,mt8183-svs-cpu-big" + operating-points-v2: OPP table hooked by SVS big CPU bank. + SVS will optimze this OPP table voltage part. + vcpu-big-supply: PMIC buck of big CPU +- svs_cci: SVS bank device node of CCI + compatible: "mediatek,mt8183-svs-cci" + operating-points-v2: OPP table hooked by SVS CCI bank. + SVS will optimze this OPP table voltage part. + vcci-supply: PMIC buck of CCI +- svs_gpu: SVS bank device node of GPU + compatible: "mediatek,mt8183-svs-gpu" + operating-points-v2: OPP table hooked by SVS GPU bank. + SVS will optimze this OPP table voltage part. + vgpu-spply: PMIC buck of GPU + +Example: + + svs: svs@...0b000 { + compatible = "mediatek,mt8183-svs"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW 0>; + clocks = <&infracfg CLK_INFRA_THERM>; + clock-names = "main_clk"; + nvmem-cells = <&svs_calibration>, <&thermal_calibration>; + nvmem-cell-names = "svs-calibration-data", "calibration-data"; + + svs_cpu_little: svs_cpu_little { + compatible = "mediatek,mt8183-svs-cpu-little"; + operating-points-v2 = <&cluster0_opp>; + }; + + svs_cpu_big: svs_cpu_big { + compatible = "mediatek,mt8183-svs-cpu-big"; + operating-points-v2 = <&cluster1_opp>; + }; + + svs_cci: svs_cci { + compatible = "mediatek,mt8183-svs-cci"; + operating-points-v2 = <&cci_opp>; + }; + + svs_gpu: svs_gpu { + compatible = "mediatek,mt8183-svs-gpu"; + power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_2D>; + operating-points-v2 = <&gpu_opp_table>; + }; + }; + + &svs_cpu_little { + vcpu-little-supply = <&mt6358_vproc12_reg>; + }; + + &svs_cpu_big { + vcpu-big-supply = <&mt6358_vproc11_reg>; + }; + + &svs_cci { + vcci-supply = <&mt6358_vproc12_reg>; + }; + + &svs_gpu { + vgpu-spply = <&mt6358_vgpu_reg>; + }; -- 2.18.0
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