linux-kernel - Re: [PATCH net-next v3 4/4] arm64: dts: fsl: ls1028a: Enable eth port1 on the ls1028a QDS board

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Date:   Mon, 29 Jul 2019 17:37:45 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Claudiu Manoil <claudiu.manoil@....com>
Cc:     "David S . Miller" <davem@...emloft.net>,
        Rob Herring <robh+dt@...nel.org>, Li Yang <leoyang.li@....com>,
        alexandru.marginean@....com, netdev@...r.kernel.org,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next v3 4/4] arm64: dts: fsl: ls1028a: Enable eth
 port1 on the ls1028a QDS board

On Mon, Jul 29, 2019 at 01:03:47PM +0300, Claudiu Manoil wrote:
> LS1028a has one Ethernet management interface. On the QDS board, the
> MDIO signals are multiplexed to either on-board AR8035 PHY device or
> to 4 PCIe slots allowing for SGMII cards.
> To enable the Ethernet ENETC Port 1, which can only be connected to a
> RGMII PHY, the multiplexer needs to be configured to route the MDIO to
> the AR8035 PHY.  The MDIO/MDC routing is controlled by bits 7:4 of FPGA
> board config register 0x54, and value 0 selects the on-board RGMII PHY.
> The FPGA board config registers are accessible on the i2c bus, at address
> 0x66.
> 
> The PF3 MDIO PCIe integrated endpoint device allows for centralized access
> to the MDIO bus.  Add the corresponding devicetree node and set it to be
> the MDIO bus parent.
> 
> Signed-off-by: Alex Marginean <alexandru.marginean@....com>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@....com>

Reviewed-by: Andrew Lunn <andrew@...n.ch>

    Andrew