linux-kernel - [PATCH v2] MIPS: Ingenic: Fix bugs when detecting X1000's parameters.

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Message-Id: <1564547943-27505-2-git-send-email-zhouyanjie@zoho.com>
Date:   Wed, 31 Jul 2019 12:39:03 +0800
From:   Zhou Yanjie <zhouyanjie@...o.com>
To:     linux-mips@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org, ralf@...ux-mips.org,
        paul@...pouillou.net, paul.burton@...s.com, jhogan@...nel.org,
        malat@...ian.org, chenhc@...ote.com, tglx@...utronix.de,
        allison@...utok.net, syq@...ian.org, jiaxun.yang@...goat.com
Subject: [PATCH v2] MIPS: Ingenic: Fix bugs when detecting X1000's parameters.

1.fix bugs when detecting L2 cache sets value.
2.fix bugs when detecting L2 cache ways value.
3.fix bugs when calculate bogoMips and loops_per_jiffy.

Signed-off-by: Zhou Yanjie <zhouyanjie@...o.com>
---
 arch/mips/include/asm/mipsregs.h |  1 +
 arch/mips/kernel/cpu-probe.c     |  7 +++++++
 arch/mips/mm/sc-mips.c           | 18 +++++++++++++++---
 3 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 1e6966e..01e0fcb 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2813,6 +2813,7 @@ __BUILD_SET_C0(status)
 __BUILD_SET_C0(cause)
 __BUILD_SET_C0(config)
 __BUILD_SET_C0(config5)
+__BUILD_SET_C0(config7)
 __BUILD_SET_C0(intcontrol)
 __BUILD_SET_C0(intctl)
 __BUILD_SET_C0(srsmap)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index eb527a1..547c9a0 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1964,6 +1964,13 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 		c->cputype = CPU_XBURST;
 		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
 		__cpu_name[cpu] = "Ingenic XBurst";
+		/*
+		 * config7 bit 4 is used to control a low-power mode in
+		 * XBurst architecture. This mode may cause errors in the
+		 * calculation of bogomips and loops_per_jiffy, set config7
+		 * bit 4 to disable this feature to prevent that.
+		 */
+		set_c0_config7(BIT(4));
 		break;
 	default:
 		panic("Unknown Ingenic Processor ID!");
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 9385ddb..ed953d4 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -215,6 +215,14 @@ static inline int __init mips_sc_probe(void)
 	else
 		return 0;
 
+	/*
+	 * According to config2 it would be 512-sets, but that is contradicted
+	 * by all documentation.
+	 */
+	if (current_cpu_type() == CPU_XBURST &&
+				mips_machtype == MACH_INGENIC_X1000)
+		c->scache.sets = 256;
+
 	tmp = (config2 >> 0) & 0x0f;
 	if (tmp <= 7)
 		c->scache.ways = tmp + 1;
@@ -225,9 +233,13 @@ static inline int __init mips_sc_probe(void)
 	 * According to config2 it would be 5-ways, but that is contradicted
 	 * by all documentation.
 	 */
-	if (current_cpu_type() == CPU_XBURST &&
-				mips_machtype == MACH_INGENIC_JZ4770)
-		c->scache.ways = 4;
+	if (current_cpu_type() == CPU_XBURST) {
+		switch (mips_machtype) {
+		case MACH_INGENIC_JZ4770:
+		case MACH_INGENIC_X1000:
+			c->scache.ways = 4;
+		}
+	}
 
 	c->scache.waysize = c->scache.sets * c->scache.linesz;
 	c->scache.waybit = __ffs(c->scache.waysize);
-- 
2.7.4