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Message-Id: <70D536BE-8DC7-4CA2-84A9-AFB067BA520E@canonical.com>
Date: Thu, 1 Aug 2019 17:05:54 +0800
From: Kai-Heng Feng <kai.heng.feng@...onical.com>
To: "Rafael J. Wysocki" <rafael@...nel.org>
Cc: Keith Busch <kbusch@...nel.org>,
Mario Limonciello <Mario.Limonciello@...l.com>,
"Rafael J. Wysocki" <rjw@...ysocki.net>,
Keith Busch <keith.busch@...el.com>,
Christoph Hellwig <hch@....de>,
Sagi Grimberg <sagi@...mberg.me>,
linux-nvme <linux-nvme@...ts.infradead.org>,
Linux PM <linux-pm@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Rajat Jain <rajatja@...gle.com>
Subject: Re: [Regression] Commit "nvme/pci: Use host managed power state for
suspend" has problems
at 06:33, Rafael J. Wysocki <rafael@...nel.org> wrote:
> On Thu, Aug 1, 2019 at 12:22 AM Keith Busch <kbusch@...nel.org> wrote:
>> On Wed, Jul 31, 2019 at 11:25:51PM +0200, Rafael J. Wysocki wrote:
>>> A couple of remarks if you will.
>>>
>>> First, we don't know which case is the majority at this point. For
>>> now, there is one example of each, but it may very well turn out that
>>> the SK Hynix BC501 above needs to be quirked.
>>>
>>> Second, the reference here really is 5.2, so if there are any systems
>>> that are not better off with 5.3-rc than they were with 5.2, well, we
>>> have not made progress. However, if there are systems that are worse
>>> off with 5.3, that's bad. In the face of the latest findings the only
>>> way to avoid that is to be backwards compatible with 5.2 and that's
>>> where my patch is going. That cannot be achieved by quirking all
>>> cases that are reported as "bad", because there still may be
>>> unreported ones.
>>
>> I have to agree. I think your proposal may allow PCI D3cold,
>
> Yes, it may.
Somehow the 9380 with Toshiba NVMe never hits SLP_S0 with or without
Rafael’s patch.
But the “real” s2idle power consumption does improve with the patch.
Can we use a DMI based quirk for this platform? It seems like a platform
specific issue.
>
>> In which case we do need to reintroduce the HMB handling.
>
> Right.
The patch alone doesn’t break HMB Toshiba NVMe I tested. But I think it’s
still safer to do proper HMB handling.
Kai-Heng
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