linux-kernel - Re: [PATCH 4/5] media/ivtv: Reduce default FIFO priority

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Date:   Fri, 2 Aug 2019 10:58:22 +0200
From:   Peter Zijlstra <peterz@...radead.org>
To:     Andy Walls <andy@...verblocksystems.net>
Cc:     mingo@...nel.org, linux-kernel@...r.kernel.org,
        Andy Walls <awalls@...metrocast.net>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        linux-media@...r.kernel.org, Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [PATCH 4/5] media/ivtv: Reduce default FIFO priority

On Thu, Aug 01, 2019 at 02:38:06PM +0200, Peter Zijlstra wrote:
> If the consumer of the data are RT tasks as well (I hadn't expected that
> from a TV capture device) then I'd propose to use FIFO-50 as default.
> 
> The thing is, the moment you're doing actual proper RT, the admin needs
> to configure things anyway, which then very much includes setting the
> priority of interrupt threads and the like.
> 
> (that is exacty why pretty much everything defaults to FIFO-50)

Is the below acceptible?

---
Subject: media/ivtv: Reduce default FIFO priority
From: Peter Zijlstra <peterz@...radead.org>
Date: Thu Aug  1 12:56:40 CEST 2019

The ivtv driver creates a FIFO-99 thread by default, reduce this to
FIFO-50.

FIFO-99 is the very highest priority available to SCHED_FIFO and
it not a suitable default; it would indicate the ivtv work is the
most important work on the machine.

Cc: Andy Walls <awalls@...metrocast.net>
Cc: Mauro Carvalho Chehab <mchehab@...nel.org>
Cc: linux-media@...r.kernel.org
Cc: linux-kernel@...r.kernel.org
Cc: Thomas Gleixner <tglx@...utronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
---
 drivers/media/pci/ivtv/ivtv-driver.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/media/pci/ivtv/ivtv-driver.c
+++ b/drivers/media/pci/ivtv/ivtv-driver.c
@@ -738,7 +738,7 @@ static void ivtv_process_options(struct
  */
 static int ivtv_init_struct1(struct ivtv *itv)
 {
-	struct sched_param param = { .sched_priority = 99 };
+	struct sched_param param = { .sched_priority = MAX_RT_PRIO / 2 };
 
 	itv->base_addr = pci_resource_start(itv->pdev, 0);
 	itv->enc_mbox.max_mbox = 2; /* the encoder has 3 mailboxes (0-2) */