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Message-ID: <86o916mx2m.wl-maz@kernel.org>
Date: Sat, 03 Aug 2019 10:12:49 +0100
From: Marc Zyngier <maz@...nel.org>
To: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc: tglx@...utronix.de, jason@...edaemon.net, ralf@...ux-mips.org,
paul.burton@...s.com, jhogan@...nel.org, robh+dt@...nel.org,
linux-mips@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, mark.rutland@....com,
john@...ozen.org, Hauke Mehrtens <hauke@...ke-m.de>
Subject: Re: [PATCH 3/5] MIPS: lantiq: add an irq_domain and irq_chip for EBU
Hi Martin,
On Thu, 01 Aug 2019 18:42:42 +0100,
Martin Blumenstingl <martin.blumenstingl@...glemail.com> wrote:
[...]
> > > +static void ltq_ebu_irq_handler(struct irq_desc *desc)
> > > +{
> > > + struct irq_domain *domain = irq_desc_get_handler_data(desc);
> > > + struct irq_chip *irqchip = irq_desc_get_chip(desc);
> > > +
> > > + chained_irq_enter(irqchip, desc);
> > > +
> > > + generic_handle_irq(irq_find_mapping(domain, 0));
> >
> > Having an irqdomain for a single interrupt is a bit over the top... Is
> > that for the convenience of the DT infrastructure?
> yes, I did it to get DT support
> please let me know if there's a "better" way (preferably with another
> driver as example)
To be honest, the chained handler is what troubles me the most. You
normally would use such a construct if you had a multiplexer. In your
case, you have a 1:1 relationship between input and output. It is just
that this irqchip allows the trigger to be adapted, which normally
calls for a hierarchical implementation.
In your case, with only a single interrupt, it doesn't matter much
though.
>
> [...]
> > > + irq_create_mapping(domain, 0);
> >
> > Why do you need to perform this eagerly? I'd expect this interrupt to
> > be mapped when it is actually claimed by a driver.
> I don't remember why I added it, it may be left-over from copying from
> another driver
> in v2 I'll try to drop it
>
> > > +
> > > + irq_set_chained_handler_and_data(irq, ltq_ebu_irq_handler, domain);
> >
> > And there is no HW initialisation whatsoever? I'd expect, at the very
> > least, the sole interrupt to be configured as disabled/masked.
> I can add that. is there any "best practice" on what I should
> initialize (just disable it or also set a "default" mode like
> LEVEL_LOW)?
Whichever default state makes sense. What you want to avoid is to boot
the kernel with a screaming interrupt because some firmware has left
it enabled.
Thanks,
M.
--
Jazz is not dead, it just smells funny.
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