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Message-ID: <20190806143457.GF475@lakrids.cambridge.arm.com>
Date: Tue, 6 Aug 2019 15:34:57 +0100
From: Mark Rutland <mark.rutland@....com>
To: Rob Clark <robdclark@...omium.org>
Cc: Christoph Hellwig <hch@....de>, Rob Clark <robdclark@...il.com>,
dri-devel <dri-devel@...ts.freedesktop.org>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <maxime.ripard@...tlin.com>,
Sean Paul <sean@...rly.run>, David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
Allison Randal <allison@...utok.net>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Thomas Gleixner <tglx@...utronix.de>,
linux-arm-kernel@...ts.infradead.org,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] drm: add cache support for arm64
On Tue, Aug 06, 2019 at 07:11:41AM -0700, Rob Clark wrote:
> On Tue, Aug 6, 2019 at 1:48 AM Christoph Hellwig <hch@....de> wrote:
> >
> > This goes in the wrong direction. drm_cflush_* are a bad API we need to
> > get rid of, not add use of it. The reason for that is two-fold:
> >
> > a) it doesn't address how cache maintaince actually works in most
> > platforms. When talking about a cache we three fundamental operations:
> >
> > 1) write back - this writes the content of the cache back to the
> > backing memory
> > 2) invalidate - this remove the content of the cache
> > 3) write back + invalidate - do both of the above
>
> Agreed that drm_cflush_* isn't a great API. In this particular case
> (IIUC), I need wb+inv so that there aren't dirty cache lines that drop
> out to memory later, and so that I don't get a cache hit on
> uncached/wc mmap'ing.
Is there a cacheable alias lying around (e.g. the linear map), or are
these addresses only mapped uncached/wc?
If there's a cacheable alias, performing an invalidate isn't sufficient,
since a CPU can allocate a new (clean) entry at any point in time (e.g.
as a result of prefetching or arbitrary speculation).
Thanks,
Mark.
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