linux-kernel - Re: [PATCH] clk: ingenic/jz4740: Fix "pll half" divider not read/written properly

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Message-Id: <1565220490.15188.0@crapouillou.net>
Date:   Thu, 08 Aug 2019 01:28:10 +0200
From:   Paul Cercueil <paul@...pouillou.net>
To:     Stephen Boyd <sboyd@...nel.org>
Cc:     Michael Turquette <mturquette@...libre.com>,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: ingenic/jz4740: Fix "pll half" divider not
 read/written properly



Le mer. 7 août 2019 à 23:33, Stephen Boyd <sboyd@...nel.org> a écrit 
:
> Quoting Paul Cercueil (2019-07-01 04:36:06)
>>  The code was setting the bit 21 of the CPCCR register to use a 
>> divider
>>  of 2 for the "pll half" clock, and clearing the bit to use a divider
>>  of 1.
>> 
>>  This is the opposite of how this register field works: a cleared bit
>>  means that the /2 divider is used, and a set bit means that the 
>> divider
>>  is 1.
>> 
>>  Restore the correct behaviour using the newly introduced .div_table
>>  field.
>> 
>>  Signed-off-by: Paul Cercueil <paul@...pouillou.net>
>>  ---
> 
> Applied to clk-next. Does this need a fixes tag?

It depends on commit a9fa2893fcc6 ("clk: ingenic: Add support for
divider tables") which was sent without a fixes tag, so it'd be
a bit difficult. Probably not worth the trouble.

-Paul