linux-kernel - Re: [PATCH v2 4/5] firmware: arm_scmi: Add RESET protocol in SCMI v2.0

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Date:   Wed, 07 Aug 2019 10:17:50 +0200
From:   Philipp Zabel <p.zabel@...gutronix.de>
To:     Sudeep Holla <sudeep.holla@....com>,
        linux-arm-kernel@...ts.infradead.org
Cc:     Peng Fan <peng.fan@....com>, linux-kernel@...r.kernel.org,
        Bo Zhang <bozhang.zhang@...adcom.com>,
        Jim Quinlan <james.quinlan@...adcom.com>,
        Volodymyr Babchuk <volodymyr_babchuk@...m.com>,
        Gaku Inami <gaku.inami.xh@...esas.com>,
        aidapala@....qualcomm.com, pajay@....qualcomm.com,
        Etienne Carriere <etienne.carriere@...aro.org>,
        Souvik Chakravarty <Souvik.Chakravarty@....com>,
        wesleys@...inx.com, Felix Burton <fburton@...inx.com>,
        Saeed Nowshadi <saeed.nowshadi@...inx.com>
Subject: Re: [PATCH v2 4/5] firmware: arm_scmi: Add RESET protocol in SCMI
 v2.0

On Tue, 2019-08-06 at 18:02 +0100, Sudeep Holla wrote:
> SCMIv2.0 adds a new Reset Management Protocol to manage various reset
> states a given device or domain can enter. Device(s) that can be
> collectively reset through a common reset signal constitute a reset
> domain for the firmware.
> 
> A reset domain can be reset autonomously or explicitly through assertion
> and de-assertion of the signal. When autonomous reset is chosen, the
> firmware is responsible for taking the necessary steps to reset the
> domain and to subsequently bring it out of reset. When explicit reset is
> chosen, the caller has to specifically assert and then de-assert the
> reset signal by issuing two separate RESET commands.
> 
> Add the basic SCMI reset infrastructure that can be used by Linux
> reset controller driver.
> 
> Cc: Philipp Zabel <p.zabel@...gutronix.de>
> Signed-off-by: Sudeep Holla <sudeep.holla@....com>
> ---
>  drivers/firmware/arm_scmi/Makefile |   2 +-
>  drivers/firmware/arm_scmi/reset.c  | 231 +++++++++++++++++++++++++++++
>  include/linux/scmi_protocol.h      |  26 ++++
>  3 files changed, 258 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/firmware/arm_scmi/reset.c
> 
> diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi/Makefile
> index c47d28d556b6..5f298f00a82e 100644
> --- a/drivers/firmware/arm_scmi/Makefile
> +++ b/drivers/firmware/arm_scmi/Makefile
> @@ -2,5 +2,5 @@
>  obj-y	= scmi-bus.o scmi-driver.o scmi-protocols.o
>  scmi-bus-y = bus.o
>  scmi-driver-y = driver.o
> -scmi-protocols-y = base.o clock.o perf.o power.o sensors.o
> +scmi-protocols-y = base.o clock.o perf.o power.o reset.o sensors.o
>  obj-$(CONFIG_ARM_SCMI_POWER_DOMAIN) += scmi_pm_domain.o
> diff --git a/drivers/firmware/arm_scmi/reset.c b/drivers/firmware/arm_scmi/reset.c
> new file mode 100644
> index 000000000000..11cb8b5ccf34
> --- /dev/null
> +++ b/drivers/firmware/arm_scmi/reset.c
> @@ -0,0 +1,231 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * System Control and Management Interface (SCMI) Reset Protocol
> + *
> + * Copyright (C) 2019 ARM Ltd.
> + */
> +
> +#include "common.h"
> +
> +enum scmi_reset_protocol_cmd {
> +	RESET_DOMAIN_ATTRIBUTES = 0x3,
> +	RESET = 0x4,
> +	RESET_NOTIFY = 0x5,
> +};
> +
> +enum scmi_reset_protocol_notify {
> +	RESET_ISSUED = 0x0,
> +};
> +
> +#define NUM_RESET_DOMAIN_MASK	0xffff
> +#define RESET_NOTIFY_ENABLE	BIT(0)
> +
> +struct scmi_msg_resp_reset_domain_attributes {
> +	__le32 attributes;
> +#define SUPPORTS_ASYNC_RESET(x)		((x) & BIT(31))
> +#define SUPPORTS_NOTIFY_RESET(x)	((x) & BIT(30))
> +	__le32 latency;
> +	    u8 name[SCMI_MAX_STR_SIZE];
> +};
> +
> +struct scmi_msg_reset_domain_reset {
> +	__le32 domain_id;
> +	__le32 flags;
> +#define AUTONOMOUS_RESET	BIT(0)
> +#define EXPLICIT_RESET_ASSERT	BIT(1)
> +#define ASYNCHRONOUS_RESET	BIT(2)
> +	__le32 reset_state;
> +#define ARCH_RESET_TYPE		BIT(31)
> +#define COLD_RESET_STATE	BIT(0)
> +#define ARCH_COLD_RESET		(ARCH_RESET_TYPE | COLD_RESET_STATE)
> +};
> +
> +struct reset_dom_info {
> +	bool async_reset;
> +	bool reset_notify;
> +	u32 latency_us;
> +	char name[SCMI_MAX_STR_SIZE];
> +};
> +
> +struct scmi_reset_info {
> +	int num_domains;
> +	struct reset_dom_info *dom_info;
> +};
> +
> +static int scmi_reset_attributes_get(const struct scmi_handle *handle,
> +				     struct scmi_reset_info *pi)
> +{
> +	int ret;
> +	struct scmi_xfer *t;
> +	u32 *attr;
> +
> +	ret = scmi_xfer_get_init(handle, PROTOCOL_ATTRIBUTES,
> +				 SCMI_PROTOCOL_RESET, 0, sizeof(*attr), &t);
> +	if (ret)
> +		return ret;
> +
> +	attr = t->rx.buf;
> +
> +	ret = scmi_do_xfer(handle, t);
> +	if (!ret)
> +		pi->num_domains = le32_to_cpu(*attr) & NUM_RESET_DOMAIN_MASK;
> +
> +	scmi_xfer_put(handle, t);
> +	return ret;
> +}
> +
> +static int
> +scmi_reset_domain_attributes_get(const struct scmi_handle *handle, u32 domain,
> +				 struct reset_dom_info *dom_info)
> +{
> +	int ret;
> +	struct scmi_xfer *t;
> +	struct scmi_msg_resp_reset_domain_attributes *attr;
> +
> +	ret = scmi_xfer_get_init(handle, RESET_DOMAIN_ATTRIBUTES,
> +				 SCMI_PROTOCOL_RESET, sizeof(domain),
> +				 sizeof(*attr), &t);
> +	if (ret)
> +		return ret;
> +
> +	*(__le32 *)t->tx.buf = cpu_to_le32(domain);

Should this use
	put_unaligned_le32(domain, t->tx.buf);
? Either way,

Reviewed-by: Philipp Zabel <p.zabel@...gutronix.de>

regards
Philipp