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Message-ID: <9096cbca-f647-b0af-2ab8-d48769555c3e@nvidia.com>
Date: Fri, 9 Aug 2019 11:50:33 -0700
From: Sowjanya Komatineni <skomatineni@...dia.com>
To: Dmitry Osipenko <digetx@...il.com>, <thierry.reding@...il.com>,
<jonathanh@...dia.com>, <tglx@...utronix.de>,
<jason@...edaemon.net>, <marc.zyngier@....com>,
<linus.walleij@...aro.org>, <stefan@...er.ch>,
<mark.rutland@....com>
CC: <pdeschrijver@...dia.com>, <pgaikwad@...dia.com>,
<sboyd@...nel.org>, <linux-clk@...r.kernel.org>,
<linux-gpio@...r.kernel.org>, <jckuo@...dia.com>,
<josephl@...dia.com>, <talho@...dia.com>,
<linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<mperttunen@...dia.com>, <spatra@...dia.com>, <robh+dt@...nel.org>,
<devicetree@...r.kernel.org>, <rjw@...ysocki.net>,
<viresh.kumar@...aro.org>, <linux-pm@...r.kernel.org>
Subject: Re: [PATCH v8 05/21] clk: tegra: pll: Save and restore pll context
On 8/9/19 10:50 AM, Dmitry Osipenko wrote:
> 09.08.2019 20:39, Sowjanya Komatineni пишет:
>> On 8/9/19 4:33 AM, Dmitry Osipenko wrote:
>>> 09.08.2019 2:46, Sowjanya Komatineni пишет:
>>>> This patch implements save and restore of PLL context.
>>>>
>>>> During system suspend, core power goes off and looses the settings
>>>> of the Tegra CAR controller registers.
>>>>
>>>> So during suspend entry pll context is stored and on resume it is
>>>> restored back along with its state.
>>>>
>>>> Acked-by: Thierry Reding <treding@...dia.com>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@...dia.com>
>>>> ---
>>>> drivers/clk/tegra/clk-pll.c | 88 ++++++++++++++++++++++++++++-----------------
>>>> drivers/clk/tegra/clk.h | 2 ++
>>>> 2 files changed, 58 insertions(+), 32 deletions(-)
>>>>
>>>> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
>>>> index 1583f5fc992f..e52add2bbdbb 100644
>>>> --- a/drivers/clk/tegra/clk-pll.c
>>>> +++ b/drivers/clk/tegra/clk-pll.c
>>>> @@ -1008,6 +1008,28 @@ static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
>>>> return rate;
>>>> }
>>>> +static void tegra_clk_pll_restore_context(struct clk_hw *hw)
>>>> +{
>>>> + struct tegra_clk_pll *pll = to_clk_pll(hw);
>>>> + struct clk_hw *parent = clk_hw_get_parent(hw);
>>>> + unsigned long parent_rate = clk_hw_get_rate(parent);
>>>> + unsigned long rate = clk_hw_get_rate(hw);
>>>> + u32 val;
>>>> +
>>>> + if (clk_pll_is_enabled(hw))
>>>> + return;
>>>> +
>>>> + if (pll->params->set_defaults)
>>>> + pll->params->set_defaults(pll);
>>>> +
>>>> + clk_pll_set_rate(hw, rate, parent_rate);
>>>> +
>>>> + if (!__clk_get_enable_count(hw->clk))
>>> What about orphaned clocks? Is enable_count > 0 for them?
>> There are no orphaned pll clocks.
> Sorry, I meant the "clk_ignore_unused".
clocks with CLK_IGNORE_UNUSED are taken care by clk driver.
clk_disable_unused checks for clocks with this flag and if they are not
enabled it will enable them.
So by the time suspend happens enable_count is > 0
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