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Message-ID: <CAL_JsqK3c+5FzcHMNJC7RnGeMZirMT-b3NZ8yCa5Mwy=Pq53aQ@mail.gmail.com>
Date: Mon, 12 Aug 2019 13:56:50 -0600
From: Rob Herring <robh+dt@...nel.org>
To: Dmitry Osipenko <digetx@...il.com>
Cc: Michael Turquette <mturquette@...libre.com>,
Joseph Lo <josephl@...dia.com>,
Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Peter De Schrijver <pdeschrijver@...dia.com>,
Prashant Gaikwad <pgaikwad@...dia.com>,
Stephen Boyd <sboyd@...nel.org>, devicetree@...r.kernel.org,
linux-clk <linux-clk@...r.kernel.org>,
linux-tegra@...r.kernel.org,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v10 11/15] dt-bindings: memory: Add binding for NVIDIA
Tegra30 External Memory Controller
On Sun, Aug 11, 2019 at 3:01 PM Dmitry Osipenko <digetx@...il.com> wrote:
>
> Add device-tree binding for NVIDIA Tegra30 External Memory Controller.
> The binding is based on the Tegra124 EMC binding since hardware is
> similar, although there are couple significant differences.
>
> Note that the memory timing description is given in a platform-specific
> form because there is no detailed information on how to convert a
> typical-common DDR timing into the register values. The timing format is
> borrowed from downstream kernel, hence there is no hurdle in regards to
> upstreaming of memory timings for the boards.
>
> Acked-by: Peter De Schrijver <pdeschrijver@...dia.com>
> Signed-off-by: Dmitry Osipenko <digetx@...il.com>
> ---
> .../nvidia,tegra30-emc.yaml | 336 ++++++++++++++++++
> 1 file changed, 336 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml
Reviewed-by: Rob Herring <robh@...nel.org>
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