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Message-ID: <DB3PR0402MB39161E58AFF5681757DE1C06F5D30@DB3PR0402MB3916.eurprd04.prod.outlook.com>
Date: Mon, 12 Aug 2019 02:03:03 +0000
From: Anson Huang <anson.huang@....com>
To: Guenter Roeck <linux@...ck-us.net>
CC: "wim@...ux-watchdog.org" <wim@...ux-watchdog.org>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
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Subject: RE: [PATCH 1/4] dt-bindings: watchdog: Add i.MX7ULP bindings
Hi, Guenter
> On Fri, Aug 09, 2019 at 03:13:59PM +0800, Anson Huang wrote:
> > Add the watchdog bindings for Freescale i.MX7ULP.
> >
> > Signed-off-by: Anson Huang <Anson.Huang@....com>
> > ---
> > .../bindings/watchdog/fsl-imx7ulp-wdt.txt | 22
> ++++++++++++++++++++++
> > 1 file changed, 22 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt
> > b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt
> > new file mode 100644
> > index 0000000..d83fc5c
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt
> > @@ -0,0 +1,22 @@
> > +* Freescale i.MX7ULP Watchdog Timer (WDT) Controller
> > +
> > +Required properties:
> > +- compatible : Should be "fsl,imx7ulp-wdt"
> > +- reg : Should contain WDT registers location and length
> > +- interrupts : Should contain WDT interrupt
> > +- clocks: Should contain a phandle pointing to the gated peripheral clock.
>
> The driver as submitted does not include clock or interrupt handling.
> Why are those properties listed as mandatory if they are not really needed
> (nor used) ?
I missed the clk part in driver, it is working ONLY because the wdog clock is enabled
unexpected, I will add it in V2, thanks for pointing out such big mistake!
Anson
>
> > +
> > +Optional properties:
> > +- timeout-sec : Contains the watchdog timeout in seconds
> > +
> > +Examples:
> > +
> > +wdog1: wdog@...d0000 {
> > + compatible = "fsl,imx7ulp-wdt";
> > + reg = <0x403d0000 0x10000>;
> > + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
> > + assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
> > + assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
> > + timeout-sec = <40>;
> > +};
> > --
> > 2.7.4
> >
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