linux-kernel - RE: [EXT] Re: [PATCHv3 2/2] PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <AM5PR04MB3299F2291ECDB3350C4CDCE8F5D30@AM5PR04MB3299.eurprd04.prod.outlook.com>
Date:   Mon, 12 Aug 2019 10:18:59 +0000
From:   Xiaowei Bao <xiaowei.bao@....com>
To:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>
CC:     "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        Leo Li <leoyang.li@....com>, "kishon@...com" <kishon@...com>,
        "arnd@...db.de" <arnd@...db.de>,
        "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "M.h. Lian" <minghuan.lian@....com>,
        Mingkai Hu <mingkai.hu@....com>, Roy Zang <roy.zang@....com>,
        "kstewart@...uxfoundation.org" <kstewart@...uxfoundation.org>,
        "pombredanne@...b.com" <pombredanne@...b.com>,
        "shawn.lin@...k-chips.com" <shawn.lin@...k-chips.com>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>
Subject: RE: [EXT] Re: [PATCHv3 2/2] PCI: layerscape: Add
 CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately



> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
> Sent: 2019年8月12日 18:06
> To: Xiaowei Bao <xiaowei.bao@....com>
> Cc: bhelgaas@...gle.com; robh+dt@...nel.org; mark.rutland@....com;
> shawnguo@...nel.org; Leo Li <leoyang.li@....com>; kishon@...com;
> arnd@...db.de; gregkh@...uxfoundation.org; M.h. Lian
> <minghuan.lian@....com>; Mingkai Hu <mingkai.hu@....com>; Roy Zang
> <roy.zang@....com>; kstewart@...uxfoundation.org;
> pombredanne@...b.com; shawn.lin@...k-chips.com;
> linux-pci@...r.kernel.org; devicetree@...r.kernel.org;
> linux-kernel@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> linuxppc-dev@...ts.ozlabs.org
> Subject: [EXT] Re: [PATCHv3 2/2] PCI: layerscape: Add
> CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately
> 
> Caution: EXT Email
> 
> On Fri, Jun 28, 2019 at 09:38:26AM +0800, Xiaowei Bao wrote:
> > Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately.
> >
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@....com>
> > ---
> > v2:
> >  - No change.
> > v3:
> >  - modify the commit message.
> >
> >  drivers/pci/controller/dwc/Kconfig  |   20 ++++++++++++++++++--
> >  drivers/pci/controller/dwc/Makefile |    3 ++-
> >  2 files changed, 20 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/Kconfig
> > b/drivers/pci/controller/dwc/Kconfig
> > index a6ce1ee..a41ccf5 100644
> > --- a/drivers/pci/controller/dwc/Kconfig
> > +++ b/drivers/pci/controller/dwc/Kconfig
> > @@ -131,13 +131,29 @@ config PCI_KEYSTONE_EP
> >         DesignWare core functions to implement the driver.
> >
> >  config PCI_LAYERSCAPE
> > -     bool "Freescale Layerscape PCIe controller"
> > +     bool "Freescale Layerscape PCIe controller - Host mode"
> >       depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
> >       depends on PCI_MSI_IRQ_DOMAIN
> >       select MFD_SYSCON
> >       select PCIE_DW_HOST
> >       help
> > -       Say Y here if you want PCIe controller support on Layerscape SoCs.
> > +       Say Y here if you want to enable PCIe controller support on
> Layerscape
> > +       SoCs to work in Host mode.
> > +       This controller can work either as EP or RC. The
> > + RCW[HOST_AGT_PEX]
> 
> What's "The RCW" ? This entry should explain why a kernel configuration
> should enable it.
[Xiaowei Bao] Hi Lorenzo, the RCW full name is "reset configuration word", it can be built to a bin file and program to the flash, rather than configure by kernel, almost the NXP Layerscaple platform use this way.
> 
> Lorenzo
> 
> > +       determines which PCIe controller works in EP mode and which
> PCIe
> > +       controller works in RC mode.
> > +
> > +config PCI_LAYERSCAPE_EP
> > +     bool "Freescale Layerscape PCIe controller - Endpoint mode"
> > +     depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
> > +     depends on PCI_ENDPOINT
> > +     select PCIE_DW_EP
> > +     help
> > +       Say Y here if you want to enable PCIe controller support on
> Layerscape
> > +       SoCs to work in Endpoint mode.
> > +       This controller can work either as EP or RC. The
> RCW[HOST_AGT_PEX]
> > +       determines which PCIe controller works in EP mode and which
> PCIe
> > +       controller works in RC mode.
> >
> >  config PCI_HISI
> >       depends on OF && (ARM64 || COMPILE_TEST) diff --git
> > a/drivers/pci/controller/dwc/Makefile
> > b/drivers/pci/controller/dwc/Makefile
> > index b085dfd..824fde7 100644
> > --- a/drivers/pci/controller/dwc/Makefile
> > +++ b/drivers/pci/controller/dwc/Makefile
> > @@ -8,7 +8,8 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
> >  obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
> >  obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
> >  obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
> > -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o
> > +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
> > +obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o
> >  obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
> >  obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
> >  obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
> > --
> > 1.7.1
> >