lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20190813072954.GA23417@infradead.org>
Date:   Tue, 13 Aug 2019 00:29:54 -0700
From:   Christoph Hellwig <hch@...radead.org>
To:     Dan Williams <dan.j.williams@...el.com>
Cc:     Christoph Hellwig <hch@...radead.org>,
        Stephen Douthit <stephend@...icom-usa.com>,
        Jens Axboe <axboe@...nel.dk>,
        "linux-ide@...r.kernel.org" <linux-ide@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ata: ahci: Lookup PCS register offset based on PCI
 device ID

On Mon, Aug 12, 2019 at 12:31:35PM -0700, Dan Williams wrote:
> It seems platforms / controllers that fail to run the option-rom
> should be quirked by device-id, but the PCS register twiddling be
> removed for everyone else. "Card BIOS" to me implies devices with an
> Option-ROM BAR which I don't think modern devices have, so that might
> be a simple way to try to phase out this quirk going forward without
> regressing working setups that might be relying on this.
> 
> Then again the driver is already depending on the number of enabled
> ports to be reliable before PCS is written, and the current driver
> does not attempt to enable ports that were not enabled previously.
> That tells me that if the PCS quirk ever mattered it would have
> already regressed when the driver switched from blindly writing 0xf to
> only setting the bits that were already set in ->port_map.

But how do we find that out?

A compromise to me seems that we just do the PCS quirk for all Intel
devices explicitly listed in the PCI Ids based on new board_* values
as long as they have the old PCS location, and assume anything new
enough to have the new location won't need to quirk, given that it
never properly worked.  This might miss some intel devices that were
supported with the class based catchall, though.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ